• Title/Summary/Keyword: 환형 핀

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Optimization of an Annular Fin with Variable Pipe Inside Radius in the Heat Exchanger of Ground Source System (지열시스템의 열교환기에서 원 관 내부 반경이 변하는 환형 핀의 최적화)

  • Kang, Hyung-Suk
    • New & Renewable Energy
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    • v.5 no.1
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    • pp.40-46
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    • 2009
  • Optimization of a rectangular profile annular fin with variable pipe inside radius is presented. This optimum procedure is based on fixed fin height and is made by using variables separation method. The optimum heat loss, corresponding optimum fin length and optimum fin efficiency are presented as a function of pipe inside radius, fin half height, inside fluid convection characteristic number and ambient convection characteristic number. One of results shows that the optimum fin length increases linearly with increase of pipe inside radius for fixed fin height and fin base radius.

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Comparison of Heat Transfer Between 1-D and 2-D Analyses for a Rectangular Annular Fin (사각 환형 핀에 대한 1차원과 2차원 해석의 열전달 비교)

  • Kang, Hyung-Suk
    • Proceedings of the SAREK Conference
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    • 2009.06a
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    • pp.1177-1181
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    • 2009
  • Heat loss from a convective rectangular profile annular fin with variable inside fluid heat transfer coefficient and fin height is calculated by using both the one dimensional analytic method and two dimensional variables separation method. Heat loss from the two dimensional method and the relative error of heat loss between the one dimensional method and two dimensional method are presented as a function of the fin length, ambient convection characteristic number and fin height. One of the results shows that the relative error of heat loss between one dimensional method and two dimensional method is within 0.7% in the range of given parameters in this study.

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Chemical Sensors Using Polymer/Graphene Composite and The Effect of Graphene Content on Sensor Behavior (고분자/그래핀 복합재료의 센서 응용 및 그래핀 함량이 센서 거동에 미치는 영향)

  • Bae, Joonwon
    • Applied Chemistry for Engineering
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    • v.31 no.1
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    • pp.25-29
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    • 2020
  • In this study, a polymer/graphene hybrid composite was prepared by a simple roll-method and a simple sensor was produced by a convenient surface engineering procedure. The sensor performance was examined and the effect of graphene content on the sensing behavior was monitored. A polymer (polydimethylsiloxane, PDMS) paste containing graphene powder was prepared by a three-roll apparatus and polymer/graphene hybrid composite was produced by a two-roll technique. The sensing medium, cyclodextrin (CD) was introduced by a convenient bio-conjugation method. The efficacy of surface modification was confirmed by FT-IR spectroscopy and the ohmic relation was observed on composite surfaces. An analyte (e.g., methyl paraben, MePRB) at a 10 nM concnetration could be detected. When the graphene loading was low, the sensor performance was relatively poor. This was attributed to the absence of graphene alignments, which were observed for the composites having a high graphene loading. This indicates that the sensor performance was influenced by physical alignments of the filler. This article can provide important information for future research on developing sensing devices.

Topology of High Speed System Emulator and Its Software (초고속 시스템 에뮬레이터의 구조와 이를 위한 소프트웨어)

  • Kim, Nam-Do;Yang, Se-Yang
    • The KIPS Transactions:PartA
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    • v.8A no.4
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    • pp.479-488
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    • 2001
  • As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

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