• Journal of the Korean Society of Propulsion Engineers
• /
• v.7 no.1
• /
• pp.1-9
• /
• 2003

The rectangular profile annular fin with fixed volume is optimized using 2-dimensional analytic method. For a base boundary condition, convection from fluid within the pipe to the inside wall of the pipe and conduction from the inside wall of the pipe to the fin base are considered. Heat loss from the fin tip radius is not ignored. The maximum heat loss, the optimum fin tip radius and the optimum fin half thickness corresponding to the maximum heat loss are presented as a function of fin base radius, Biot number over the fin surface and Biot number within the pipe. Results show 1) the maximum heat loss increases as both Biot number over the fin surface and Biot number within the pipe increase and as fin base radius decreases 2) the optimum fin thickness increases as Biot number within the pipe decreases or as fin base radius and Biot number over the fin surface increase.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.2
• /
• pp.91-103
• /
• 2002

For massive FPGA based emulator, the interconnection architecture and the transmission method of signals between FPGA's are important elements which decide speed of emulation and extendability of emulator. Existing FPGA-based emulation system is faced the problems of which the emulation speed getting slow drastically as the complexity of circuit increases. In this paper, we proposed a new innovative emulation architecture that has high resource usage rate and makes the fast emulation Possible. The emulator with very unique hierarchical ring topology Presented here has merits to overcome FPGA pin limitation by connecting each FPGA into a set of pipelined rings, and it also makes emulation speed at the tens of MHz at least even at system level where the verification complexity can easily exceed the verification capability of designers.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.10C
• /
• pp.999-1007
• /
• 2002

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

• The KIPS Transactions:PartA
• /
• v.8A no.4
• /
• pp.479-488
• /
• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.21 no.3
• /
• pp.331-341
• /
• 2018

This study proposes an integrated serial spring-damper mechanism as a dual pulse generation system. Compared to the traditional dual pulse generation system, which used multiple springs and a damper to generate a dual pulse critical for impact testing of naval equipments, currently used separated serial spring-damper mechanism is comprised of two components: an air spring, and a damper. The proposed mechanism combines the two components into one integrated system with a unique design that lets simply changing the volume and the pressure of the air tank, and the length of the annular pipe adjust the stiffness and damping constants for testing, eliminating the need to have multiple sets of air springs and dampers. Simulations using MatLab and Simulink were conducted to verify the feasibility of this design. The results show the potential of an integrated serial spring-damper mechanism as a more convenient and flexible mechanism for dual pulse generation system.