• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1815-1827
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• 1993

In this paper, we evaluate the performance of a Futurebus based multiprocessor system with MESI cache coherence protocol for four bus transaction types. Graphical symbols and compiler of SLAM II are used in modeling and simulation. A steady-state probability of each state for MESI protocol is computed by a Markov chain. The probability of each state is used as an input value for a correct simulation. Processor utilization, memory utilization, bus utilization, and the waiting time for bus arbitration are measured in terms of the number of processors, the hit ratio of cache memory, the probability of internal operation, and bus bandwidth.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.25-33
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• 2014

This paper proposes a power-efficient scheduling scheme that stochastically minimizes the power consumption of real-time tasks while meeting their deadlines on multicore processors. In the proposed scheme, uncertain computation amounts of given tasks are translated into probabilistic computation amounts based on their past completion amounts, and the mean power consumption of the translated probabilistic computation amounts is minimized with a finite set of discrete clock frequencies. Also, when system load is low, the proposed scheme activates a part of all available cores with unused cores powered off, considering the leakage power consumption of cores. Evaluation shows that the scheme saves up to 69% power consumption of the previous method.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.24-26
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• 1999

본 논문에서는 주어진 윈도우에 대하여 수퍼스칼라 프로세서의 하드웨어를 구성하는 기본 요소인 인출율과 연산 유닛의 개수로 표현되는 성능 예측 모델을 제시하였다. 이때, 수퍼스칼라 프로세서에서 실행되는 벤치마크 프로그램은 매 싸이클당 각 명령어 개수가 시행되는 확률과 분기 예측 정확도에 의하여 특성화된다. 초기의 실험으로 각종 파라미터를 획득한 후에는 다양한 연산유닛과 인출율을 갖는 수퍼스칼라 프로세서의 성능을 본 논문에서 제안하는 모델에 의하여 간단하게 구할 수 있다. 명령어 자취 모의실험(trace-driven simulation)으로 측정한 성능과 본 논문에서 제안하는 성능 예측 모델에 의한 성능을 비교한 결과, 3.8%의 평균오차를 기록하였다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.31-39
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• 2013

In this paper, we propose a power-efficient scheduling scheme that stochastically minimizes the power consumption of a real-time parallel task while meeting the deadline on multicore processors. The proposed scheme applies the parallel processing that executes a task on multiple cores concurrently, and activates a part of all available cores with unused cores powered off, in order to save power consumption. It is proved that the proposed scheme minimizes the mean power consumption of a real-time parallel task with probabilistic computation amount on DVFS-enabled multicore processors with a finite set of discrete clock frequencies. Evaluation shows that the proposed scheme saves up to 81% power consumption of the previous method.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.503-506
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• 1998

본 연구에서는 방대한 양의 데이터를 실시간으로 처리하기 위한 병렬 고속 디지털 신호처리시스템을 제안한다. 시스템의 성능을 평가할 수 있는 확률적인 분석방법을 제시하며, FFT 와 같이 보드간 또는 프로세서간 통신부담이 많은 알고리즘과 행렬연산과 같이 통신부담이 적은 알고리즘에 적용하여 본다. 제안한 시스템의 다양한 구성에 대하여 두 가지 알고리듬의 성능을 확률적 방법으로 평가하였으며, 그 결과는 알고리즘 분석에 듸한 성능수치와 근접함을 확인하였다. FFT는 프로세서 개수가 증가해도 보드수가 많아지면 성능이 감소하였으며, 행렬연산은 프로세서 개수에 비례하여 시스템의 성능이 선형적으로 증가함을 확인하였다.

• The Journal of the Acoustical Society of Korea
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• v.14 no.1E
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• pp.14-21
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• 1995

This paper presents a parallel sorting algorithm suitable for the SIMD multiprocessor. The algorithm finds pivots for partitioning the data into ordered subsets. The data can be evenly distributed to be sorted since it uses the probability theory. For n data elements to be sorted on p processors, when $n{\geq}p^2$, the algorithm is shown to be asymptotically optimal. In practice, sorting 8 million data items on 64 processors achieved a 48.43-fold speedup, while the PSRS required a 44.4-fold speedup. On a variety of shared and distributed memory machines, the algorithm achieved better than half-linear speedups.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.612-614
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• 2000

하이퍼큐브의 성능을 좌우하는 중요한 요소 중 하나가 프로세서간의 통신이다. 그리고 병렬 컴퓨터에서 프로세서의 수가 증가함에 따라, 구성요소들이 오류가 날 확률도 높아졌다. 이러한 이유로, 오류 난 구성요소들이 있어도 다중 전송이 가능하게 효율적으로 설계하는 것이 중요하다. 본 논문에서는 최근에 제안된 완전 도달성 정보와 새로 추가한 국지적 정보를 이용해서 라우팅 알고리즘을 제안하고, 이것을 바탕으로 다중 전송 성공률이 높은 새로운 다중 전송 알고리즘을 제안하였다. 시뮬레이션을 통하여 제안한 기법은 기존의 기법 보다 통신량의 차이는 거의 없으면서, 다중 전송 성공률이 목적지 노드 수에 따라 5~15% 가량 향상시킬 수 있었다.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.3
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• pp.527-534
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• 2023

Triple modular redundancy (TMR) systems can continue their mission by virtue of their structural redundancy even if one processor is attacked by faults. In this paper, we propose a new fault tolerance strategy by introducing checkpoints into the TMR system in which data saving and fault detection processes are separated while they corporate together in the conventional checkpoints. Faults in one processor are tolerated by synchronizing the state of three processors upon detecting faults. Simultaneous faults occurring to more than one processor are tolerated by re-executing the task from the latest checkpoint. We propose the checkpoint placement and fault detection strategy to maximize the probability of successful execution of a task within the given deadline. We develop the Markov chain model for the TMR system having the proposed checkpoint strategy, and derive the optimal fault detection and checkpoint interval.

• The Journal of the Acoustical Society of Korea
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• v.20 no.8
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• pp.67-73
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• 2001

The shallow-water environment presents additional challenges arising from the complex interaction patterns of the sound with the sea bed. In order to overcome the difficulties generated by shallow-water propagation, broad-band matched field processing has been employed in an effort to increase robustness by utilizing multiple frequency information. In this paper, a coherent broad-band matched field processor is introduced that incorporates the spatial coherence of the acoustic field not only over one frequency but across frequencies. The incoherent and coherent processors are applied to the experimental data where it is shown that both processors give a high probability of correct localization. Also it is found that a coherent processor has better performance in the sidelobe pattern of ambiguity surfaces.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.57-68
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• 1993

In this paper, we describe a multiprocessor system using the HiPi bus with pended protocol and multiple cache memories, and evalute the performance of the multiprocessor system in terms of processor utilization for various cache coherence protocols. The HiPi bus is delveloped as the shared bus of TICOM II which is a main computer system to establish a nation-wide computing network in ETRI. The HiPi bus has high data transfer rate, but it doesn't allow cache-to-cache transfer. In order to evaluate the effect of cache-to-cache transfer upon the performance of system and to choose a best-performed protocol for HiPi bus, we simulate as follows: First, we analyze the performance of multiprocessor system with HiPi bus in terms of processor utilizatIOn through simulation. Each of cache coherence protocol is described by state transition diagram, and then the probability of each state is calculated by Markov steady state. The calculated probability of each state is used as input parameters of simulation, and modeling and simulation are implemented and performed by using SLAM II graphic symbols and language. Second, we propose the HiPi bus which supports cache-to-cache transfer, and analyze the performance of multiprocessor system with proposed HiPi bus in terms of processor utilization through simulation. Considered cache coherence protocols for the simulation are Write-through, Write-once, Berkely, Synapse, Illinois, Firefly, and Dragon.