• The KIPS Transactions:PartD
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• v.8D no.3
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• pp.233-240
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• 2001

As software technology is in progress and software quantification is getting more important, many metrics have been proposed to quantify a variety of system entities. These metrics can be classified into two different forms : scalar metric and metric vector. Though some recent studies pointed out the composition problem of the scalar metric form, many scalar metrics are successfully used in software development organizations due to their practical applications. In this paper, it is concluded that hybrid metric form weighting external complexity is most suitable for scalar metric form. With this concept, a general framework for hybrid metrics construction independent of the development methodologies and target system type is proposed. This framework was successfully used in two projects that quantify the analysis phase of the structured methodology and the design phase of the object oriented real-time system, respectively. Any organization can quantify system entities in a short time using this framework.

• The Journal of Korean Association of Computer Education
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• v.8 no.5
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• pp.129-137
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• 2005

Criticality prediction models that identify fault-prone spots using system design specifications play an important role in reducing development costs of large systems such as telecommunication systems. Many criticality prediction models using complexity metrics have been suggested. But most of them need training data set for model training. And they are classification models that can only classify design entities into fault-prone group and non fault-prone group. To solve this problem, this paper builds a new prediction model, HMM, using two styled hybrid metrics. HMM has strong point that it does not need training data and it enables comparison between design entities by criticality. HMM is implemented and compared with a well-known prediction model, BackPropagation neural network Model(BPM), considering internal characteristics and accuracy of prediction.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.