• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.7
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• pp.378-388
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• 2000

In this paper, we propose Fuzzy Polynomial Neural Networks(FPNN) based on Polynomial Neural Networks(PNN) and Fuzzy Neural Networks(FNN) for model identification of complex and nonlinear systems. The proposed FPNN is generated from the mutually combined structure of both FNN and PNN. The one and the other are considered as the premise part and consequence part of FPNN structure respectively. As the consequence part of FPNN, PNN is based on Group Method of Data Handling(GMDH) method and its structure is similar to Neural Networks. But the structure of PNN is not fixed like in conventional Neural Networks and self-organizing networks that can be generated. FPNN is available effectively for multi-input variables and high-order polynomial according to the combination of FNN with PNN. Accordingly it is possible to consider the nonlinearity characteristics of process and to get better output performance with superb predictive ability. As the premise part of FPNN, FNN uses both the simplified fuzzy inference as fuzzy inference method and error back-propagation algorithm as learning rule. The parameters such as parameters of membership functions, learning rates and momentum coefficients are adjusted using genetic algorithms. And we use two kinds of FNN structure according to the division method of fuzzy space of input variables. One is basic FNN structure and uses fuzzy input space divided by each separated input variable, the other is modified FNN structure and uses fuzzy input space divided by mutually combined input variables. In order to evaluate the performance of proposed models, we use the nonlinear function and traffic route choice process. The results show that the proposed FPNN can produce the model with higher accuracy and more robustness than any other method presented previously. And also performance index related to the approximation and prediction capabilities of model is evaluated and discussed.

• The KIPS Transactions:PartD
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• v.19D no.2
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• pp.151-160
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• 2012

Most of the distributed high-dimensional indexing structures provide a reasonable search performance especially when the dataset is uniformly distributed. However, in case when the dataset is clustered or skewed, the search performances gradually degrade as compared with the uniformly distributed dataset. We propose a method of improving the k-nearest neighbor search performance for the distributed vector approximation-tree based on the strongly clustered or skewed dataset. The basic idea is to compute volumes of the leaf nodes on the top-tree of a distributed vector approximation-tree and to assign different number of bits to them in order to assure an identification performance of vector approximation. In other words, it can be done by assigning more bits to the high-density clusters. We conducted experiments to compare the search performance with the distributed hybrid spill-tree and distributed vector approximation-tree by using the synthetic and real data sets. The experimental results show that our proposed scheme provides consistent results with significant performance improvements of the distributed vector approximation-tree for strongly clustered or skewed datasets.

• The KIPS Transactions:PartB
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• v.16B no.5
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• pp.367-376
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• 2009

In this paper, we propose a flame detection method using Haar wavelet and moving averages in outdoor infrared video sequences. Our proposed method is composed of three steps which are Haar wavelet decomposition, flame candidates detection, and their tracking and flame classification. In Haar wavelet decomposition, each frame is decomposed into 4 sub- images(LL, LH, HL, HH), and also computed high frequency energy components using LH, HL, and HH. In flame candidates detection, we compute a binary image by thresholding in LL sub-image and apply morphology operations to the binary image to remove noises. After finding initial boundaries, final candidate regions are extracted using expanding initial boundary regions to their neighborhoods. In tracking and flame classification, features of region size and high frequency energy are calculated from candidate regions and tracked using queues, and we classify whether the tracked regions are flames by temporal changes of moving averages.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.3
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• pp.45-55
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• 2000

In this paper, we proposed the hardware architecture of wavelet transform digital filter for an image processing. Filter bank pyramid algorithm is used for wavelet transform and each fillet is implemented by the FIR filter. For DWT computation, because the memory controller is implemented by hardware, we can efficiently process the multisolution decomposition of the image data only input the parameter. As a result of the image Processing in this paper, 33㏈ PSNR has been obtained on 512$\times$512 B/W image due to 11-bit mantissa processing in FPGA Implementation. And because of using QMF( Quadrature Mirror Filter) properties, it reduces half number of the multiplier needed DWT(Discrete Wavelet Transform) computation so the hardware size is reduced largely. The proposed scheme can increase the efficiency of an image Processing as well as hardware size reduced. The hardware design proposed of DWT fillet bank is synthesized by VHDL coding and then the test board is manufactured, the operating Program and the application Program are implemented using MFC++ and C++ language each other.

• Geophysics and Geophysical Exploration
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• v.10 no.1
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• pp.44-49
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• 2007

It is difficult to obtain high-resolution images by 3D gravity inversion, because the problem is extremely underdetermined - there are too many model parameters. In order to reduce the number of model parameters we propose a 3D gravity inversion scheme utilising Euler deconvolution as a priori information. The essential point of this scheme is the reduction of the nonuniqueness of solutions by restricting the inversion space with the help of Euler deconvolution. We carry out a systematic exploration of the growing body process, but only in the restricted space within a certain radius of the Euler solutions. We have tested our method with synthetic gravity data, and also applied it to a real dataset, to delineate underground cavities in a limestone area. We found that we obtained a more reasonable subsurface density image by means of this combination between the Euler solution and the inversion process.

• Convergence Security Journal
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• v.12 no.4
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• pp.17-23
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• 2012

Recently, the research for cryptographic algorithm, in particular, a stream cipher has been actively conducted for wireless devices as growing use of wireless devices such as smartphone and tablet. LFSR based random number generator is widely used in stream cipher since it has simple architecture and it operates very fast. However, the conventional multi-LFSR RNG (random number generator) suffers from its hardware complexity as well as very closed correlation between the numbers generated. A leap-ahead LFSR was presented to solve these problems. However, it has another disadvantage that the maximum period of the generated random numbers are significantly decreased according to the relationship between the number of the stages of the LFSR and the number of the output bits of the RNG. This paper presents new leap-ahead LFSR architecture to prevent this decrease in the maximum period by applying segmentation technique to the conventional leap-ahead LFSR. The proposed architecture is implemented using VHDL and it is simulated in FPGA using Xilinx ISE 10.1, with a device Virtex 4, XC4VLX15. From the simulation results, the proposed architecture has only 20% hardware complexity but it can increases the maximum period of the generated random numbers by 40% compared to the conventional Leap-ahead archtecture.

• Journal of the Korea Computer Graphics Society
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• v.25 no.5
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• pp.11-20
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• 2019

With the development of deep learning technology, research is being actively carried out on user-friendly interfaces that are suitable for use in virtual reality or augmented reality applications. To support the interface using the user's hands, this paper proposes a deep learning-based fingertip detection method to enable the tracking of fingertip coordinates to select virtual objects, or to write or draw in the air. After cutting the approximate part of the corresponding fingertip object from the input image with the Grad-CAM, and perform the convolution neural network with Atrous Convolution for the cut image to detect fingertip location. This method is simpler and easier to implement than existing object detection algorithms without requiring a pre-processing for annotating objects. To verify this method we implemented an air writing application and showed that the recognition rate of 81% and the speed of 76 ms were able to write smoothly without delay in the air, making it possible to utilize the application in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.