• The Korean Publising Journal, Monthly
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• s.328
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• pp.15-15
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• 2003

• The Korean Publising Journal, Monthly
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• s.328
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• pp.12-14
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• 2003

• The Korean Publising Journal, Monthly
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• s.328
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• pp.10-10
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• 2003

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1301-1306
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• 2010

The protocol based on password have very important qualifications that not only satisfy against attacks cause of restricting that have, but also efficiency of reducing users' workload. It has a problem of speculative attacks for the user authentication protocol based on password with most case, because users use password that can remember easily. Song and Etc. have proposed new mechanism that improved the problem of S/KEY system. The protocol proposed by Song has a problem in registration process, and user information can be abused by the malevolent server. We propose a new authentication protocol based on efficient OPT, that improved above problems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.209-214
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• 2003

Multi-mode coding method is a reliable DC-suppression method. There are two ways to improve the DC-suppression performance. One is improving scrambler's performance, and the other is improving selection criteria. The latter uses the MRDS(minimum running digital sum) criterion. It is easy to calculate, but its performance goes down when the length of codeword is getting longer. The MSW(mean squared weight) criterion that is known as the best so far regardless of the length of codeword has the high complexity. In this paper, we present the new selection criteria, MPRDS(minimum peak RDS) and A BSRDS(absolute RDS). Their performance are close to the MSW, implementation is simple. And also we present the SC(sign change) that has a subsidiary role with the original selection criteria and improve the capacity.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.280-283
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• 2003

어레이 셀 내의 연산에 대한 고성능 처리는 시스톨릭 어레이의 중요한 특징이다. 본 논문에서는 시스톨릭 어레이 구조 내 셀이 또 다른 시스톨릭 어레이 구조를 가지는 슈퍼 시스톨릭 어레이 구조를 제안하고, 그 예로 비트 레블 슈퍼 시스톨릭 정렬기의 설계 및 구현에 대하여 기술한다. 먼저 정규순환방정식으로 표현된 정렬 알고리즘으로부터 워드 레블 1차원 평면 시스톨릭 어레이를 유도한 후 유도된 워드 레블 시스톨릭 어레이를 슈퍼 시스톨릭 어레이로 변환한다. 위의 과정으로 유도된 비트 레블 슈퍼 시스톨릭 정렬기를 RT수준에서 VHDL로 모델링 하여 동작을 검증하였으며, 검증된 비트 레블 슈퍼 시스톨릭 정렬기는 Hynix에서 제공되는 0.35$\mu\textrm{m}$ 셀 라이브러리와 FPGA V200E칩을 사용하여 합성 및 구현되었다.

• Review of KIISC
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• v.32 no.6
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• pp.23-28
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• 2022

모바일 인스턴트 메신저에 적용된 암호기술은 사용자들의 개인정보를 보호하는 역할을 한다. 메신저에 저장된 사용자의 개인정보는 일반적으로 사용자의 패스워드, 사용자 정보 및 기기 정보 기반으로 생성된 암호화 키를 통해 암호화되므로 높은 안전성을 갖는다. 이러한 암호기술의 특성 때문에 국가 법집행기관은 범죄단서 확보 및 사실 증명을 위한 증거 분석과정에 어려움을 겪는다. 그러나, 최근 모바일 인스턴트 메신저를 통해 발생하고 있는 일련의 범죄 사건들을 볼 때 정당한 접근 하에 범죄단서 확보를 위한 암호분석 기술은 활발히 연구될 필요가 있다. 본 논문에서는 10종의 모바일 인스턴트 메신저에 대한 TMTO 및 GAN 모델을 활용한 안전성 분석을 제시한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.237-243
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• 2014

In this paper, we have proposed a system for creating business rules efficient in the market the SI industry. It has implemented a system that will have to be able to than to create a rule using the PPT and word simply, to proceed more smoothly communication of civil service staff and between developers. The system used in this paper, it was an object of the invention is to present a template, so as to create a document to match this template. The presented combined input tools to present a template for creating a document themes business rules to allow explicitly enter text in response to the template user.

• Journal of The Korean Association of Information Education
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• v.23 no.2
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• pp.131-139
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• 2019

From 2019, software education has become a required subject for all elementary school students. However, many teachers are still unfamiliar with how the classes should be instructed. So this paper presented the meaning, detailed competencies and achievement standard in order to help in the collection, analysis and representation of data among the computational thinking that are key to software education. And it also suggested the applicability of the classes. The full course of the paper is summarized as follows. First, existing studies have summarized the meaning, detail and achievement standard of data related competencies. Based on this, a preliminary investigation was instructed. Pilot study carried out both FGI and closed questions at the same time. This was done in response to the survey's questionnaire reflecting the opinions of experts. Second, the results of the questionnaire generated as a result of the above were verified for validity, stability, and reliability among the PhD, PhD courses, software education teachers, and software education workers. Third, I developed and applied the five lessons as a class objective as 'Choosing collection method-Select the collection method according to the problem situation.', 'Searching for meaning of data-Understand what the analyzed data mean..', 'Using various expression methods-Use a variety of expression tools.' using the backward design model to integrate education, class, and assessment. As a result, the detailed competencies of data collection, analysis, and representation and achievement standard were presented. This may help in setting specific and specific criteria for what direction classes are recommended when planning data-related classes in elementary schools.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.