• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.2
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• pp.274-279
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• 2009

H.264 suggests applying a 2-D 6-tap wiener filter to realize the interpolation for half-pixel positions, followed by a bilinear interpolation to get the data of quarter-pixels precision. This method is comparatively simpler; however, it only considers the affection of 4-connection neighborhood ignoring the influence that comes from the changing rate between respective neighborhoods. As a result, it has the characteristics of a Low-pass filter under the risk of losing high-frequency weights. The Cubic interpolation uses the gray-values within the larger regions of points to be sampled for interpolation. Nevertheless, the cubic interpolation is more complicated and computational. We give a deep analysis on the features while applying both bilinear and cubic interpolation in H.264 presenting a proper selection of interpolation algorithm with respect to specific distribution of gray-value in a certain grand block. The experiments point out that load far motion searching and interpolation are reduced when promoting the precision of interpolation simultaneously.

• Journal of Broadcast Engineering
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• v.14 no.2
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• pp.253-264
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• 2009

This paper presents an algorithm, aims at practical applications, for the high speed processing and performance enhancement of lane detection base on vision processing system. As a preprocessing for high speed lane detection, the vanishing line estimation and the optimal extraction of region of interest for lane boundary (ROI-LB) can be processed to reduction of detection region in which high speed processing is enabled. Image feature information is extracted only in the ROI-LB. Road lane is extracted using a non-parametric model fitting and Hough transform within the ROI-LB. With simultaneous processing of noise reduction and edge enhancement using the Laplacian filter, the reliability of feature extraction can be increased for various road lane patterns. Since outliers of edge at each block can be removed with clustering of edge orientation for each block within the ROI-LB, the performance of lane detection can be greatly improved. The various real road experimental results are presented to evaluate the effectiveness of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6C
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• pp.585-593
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• 2007

For the improvement of coding efficiency, the H.264 standard uses new coding tools such as VBS, 1/4-pel accurate ME, multiple references, intra prediction, loop filter, etc. Using these coding tools, H.264 has achieved significant improvements from rate-distortion point of view compared to existing standards. However, the encoder complexity is greatly increased due to these coding tools. We focus on the complexity reduction method of intra-mode decision. Our algorithm first restricts selective prediction modes of Intra4x4 using a simple preprocessing. The prediction modes of Intra4x4 are used for restricting those of the other inter-modes. Simulation results show that the proposed method outperforms other conventional methods and save about 82% of total encoding time.

• The KIPS Transactions:PartB
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• v.18B no.5
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• pp.265-270
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• 2011

In this paper, we propose a method for intensity correction using binarization-based region segmentation in 3D stereoscopic images. In the proposed method, 3D stereoscopic right image is segmented using binarizarion. Small regions in the segmented image are eliminated. For each region in right image, a corresponding region in left image is decided through region matching using correlation coefficient. When region-based matching, in order to prevent overlap between regions, we remove a portion of the area closed to the region boundary using morphological filter. The intensity correction in left and right image can be performed through histogram specification between the corresponding regions. Simulation results show the proposed method has the smallest matching error than the conventional method when we generate the right image from the left image using block based motion compensation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.1
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• pp.59-68
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• 2000

This paper proposes efficient VLSI architectures for computation of the 2- D discrete wavelet transform (DWT). The two proposed VLSI architectures for the 2- D DWT are constructed based on block-based computation Each $M{\times}N$ ($N{\times}M$) block DWT is performed along the row (column) direction simultaneously, where M and N denote the number of filter taps and the number of columns (rows), respectively The proposed architectures compute the lowpass and highpass output sequences of the 1 - DWT along the row and column directions using a single architecture In alternate clock cycles Therefore the extra processing units required for the proposed architectures are much smaller than those of the conventional architectures They are modeled In very high speed Integrated circuit hardware description language (HIDL) and Simulated to show their functional validity.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.6
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• pp.96-103
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• 1999

This paper proposes efficient VLSI architecture for computation of the 1-D discrete wavelet transform (DWT). The proposed VLSI architecture computes the wavelet lowpass and highpass output sequences using the product term anhm, $n,m{\ge}0$, where an and hm denote the imput sequence and the wavelet lowpass filter coefficient, respectively. Whereas the conventional architectures compute the lowpass and highpass output sequences using the product terms anhm and angm, respectively, where gm denotes the wavelet highpass filter coefficient. The proposed architecture is applied to computation of the Daubechies 4-tap wavelet transform using the relationships between the Daubechies wavelet filter coefficients. Performance comparison of various architectures for computation of the 1-D DWT are presented. Note that the proposed architecture does not require extra processing units whereas the conventional architectures need them. Also it is modeled in very high speed integrated circuit hardware description language (VHDL) and simulated to show its functional validity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.5
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• pp.409-419
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• 2013

Kinect released by Microsoft in November 2010 is a motion sensing camera in xbox360 and gives depth and color images. However, Kinect camera also generates holes and noise around object boundaries in the obtained images because it uses infrared pattern. Also, boundary flickering phenomenon occurs. Therefore, we propose a real-time virtual-view video synthesis algorithm which results in a high-quality virtual view by solving these problems. In the proposed algorithm, holes around the boundary are filled by using the joint bilateral filter. Color image is converted into intensity image and then flickering pixels are searched by analyzing the variation of intensity and depth images. Finally, boundary flickering phenomenon can be reduced by converting values of flickering pixels into the maximum pixel value of a previous depth image and virtual views are generated by applying 3D warping technique. Holes existing on regions that are not part of occlusion region are also filled with a center pixel value of the highest reliability block after the final block reliability is calculated by using a block based gradient searching algorithm with block reliability. The experimental results show that the proposed algorithm generated the virtual view image in real-time.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.5
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• pp.232-242
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• 2005

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in BFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9C
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• pp.1258-1268
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• 2004

We propose a new fast, algorithm which is used for detecting frontal face in the frequency domain based on human skin-color using OCT coefficient of dynamic image compression and skin color information. The region where each pixel has a value of skin-color were extracted from U and V value based on DCT coefficient obtained in the process of Image compression using skin-color map in the Y, U, V color space A morphological filter and labeling method are used to eliminate noise in the resulting image We propose the algorithm to detect fastly human face that estimate the directional feature and variance of luminance block of human skin-color Then Extraction of face was completed adaptively on both background have the object analogous to skin-color and background is simple in the proposed algorithm The performance of face detection algorithm is illustrated by some simulation results earned out on various races We confined that a success rate of 94 % was achieved from the experimental results.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.151-161
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• 2009

Audio Video Standard (AVS) is the audio and video compression standard that was developed for domestic video applications in China. AVS employs low complexity tools to minimize degradation of RD performance of the state-the-art video codec, H.264/AVC. The AVS video codec consists of $8{\times}8$ block prediction and the same size transform to improve compression efficiency for VGA and higher resolution sequences. Currently, the AVS has been adopted more and more for IPTV services and mobile applications in China. So, many consumer electronics companies and multimedia-related laboratories have been developing applications and chips for the AVS. In this paper, we implemented the AVS video decoder and optimize it on TI's Davinci EVM DSP board. For improving the decoding speed and clocks, we removed unnecessary memory operations and we also used high-speed VLD algorithm, linear assembly, intrinsic functions and so forth. Test results show that decoding speed of the optimized decoder is $5{\sim}7$ times faster than that of the reference software (RM 5.2J).