• Title/Summary/Keyword: 플래시 저장 장치

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SQLite Multi-version Concurrency Control using X-FTL (X-FTL 을 활용한 SQLite 다중버전 동시성 제어)

  • Lee, Jong-Baeg;Oh, Gi-Hwan;Lee, Sang-Won
    • Proceedings of the Korea Information Processing Society Conference
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    • 2014.11a
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    • pp.794-797
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    • 2014
  • 스마트 디바이스의 사용량 증가와 더불어 각종 가전기기의 스마트화로 인하여 임베디드 시스템에서 주로 사용되는 SQLite 데이터베이스에 대한 동시적 접근 제어의 중요성이 증가하였다. 플래시 메모리 저장장치 단계에서 트랜잭션의 원자성올 제공하는 X-FTL 은 SQLite 의 저널링 모드에서 발생하는 쓰기 연산으로 인한 성능 저하를 해결하였다. 또한 페이지 단위로 트랜잭션의 원자성을 관리하는 X-FTL 의 특징을 이용한다면 동시성 제어 측면의 성능 향상을 기대할 수 있다. 본 논문에서는 X-FTL 을 사용할 때 발생할 수 있는 동시성 제어 성능의 한계를 밝히고, X-FTL 의 X-L2P 테이블에 SCN 을 추가하여 SQLite 의 동시성 제어 성능을 향상할 수 있는 새로운 구조를 제안한다.

Improving tree index on SSD using access frequency (접근 빈도에 기반을 둔 SSD에서의 트리 인덱스 개선)

  • Choi, Won-Ki;Shin, Min-Cheol;Park, Sang-Hyun
    • Proceedings of the Korea Information Processing Society Conference
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    • 2014.11a
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    • pp.763-766
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    • 2014
  • 플래시 메모리는 입출력 속도가 빠르고 에너지 효율성이 좋지만, out-place update만 가능하며 쓰기 연산을 위한 IO의 지연시간이 읽기 연산보다 현저히 길다는 단점을 가진다. 이를 보완하기 위해 고안된 FlashSSD(Solid State Drive)는 최근 하드 디스크를 대체하는 저장장치로 주목받고 있다. DBMS(Database Management System)의 성능 개선을 위하여 FlashSSD를 활용한 다양한 연구가 진행되었다. 그중 FD-tree를 사용한 인덱스는 좋은 갱신 성능을 보임과 동시에 검색 성능을 보인다. 하지만 FD-tree의 구성 요소 중 하나인 레벨이 하나의 자료구조로만 이루어져 있어 인덱스로서의 비효율성을 가지고 있기 때문에 이를 인덱스의 접근 빈도를 이용하여 개선하고 검색 성능을 높이고자 한다.

SWSC(Sequential Write Spatial Clock) Buffer Replacement Algorithm For Mobile Flash Storage (모바일 플래시 저장장치를 위한 SWSC(Sequential Write Spatial Clock) 버퍼 교체 알고리즘)

  • Lee, Mikyung;Lee, Duki;Shin, Mincheol;Park, Sanghyun
    • Proceedings of the Korea Information Processing Society Conference
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    • 2014.11a
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    • pp.771-774
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    • 2014
  • 지난 몇 년간 스마트폰은 굉장히 빠른 속도로 발전하면서 생활 속에서 큰 비중을 차지하고 있다. 이러한 스마트폰에는 에너지 효율, 크기, 속도 면에서 모바일 기기에 적합한 Flash storage가 탑재되고 있다. 이 논문에서는 스마트폰에 탑재된 Flash storage를 기반으로 한 버퍼 교체 알고리즘들 가운데 Spatial Clock 알고리즘에 초점을 맞추고 있다. 그리고 이 알고리즘이 Video Streaming workload에서 성능 발휘를 하지 못한다는 점을 해결하기 위해 SWSC(Sequential Write Spatial Clock) 알고리즘을 제안하였다. 이 알고리즘은 dirty 페이지들이 연속적인 경우 sequential write를 수행한다. 따라서 write 수행시간을 줄일 수 있고 결과적으로 Video Streaming workload에서도 좋은 성능을 발휘할 수 있다.

An Efficient WLAN Device Power Control Technique for Streaming Multimedia Contents over Mobile IP Storage (모바일 IP 스토리지 상에서 멀티미디어 컨텐츠 실행을 위한 효율적인 무선랜 장치 전력제어 기법)

  • Nam, Young-Jin;Choi, Min-Seok
    • The KIPS Transactions:PartA
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    • v.16A no.5
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    • pp.357-368
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    • 2009
  • Mobile IP storage has been proposed to overcome storage limitation in the flash memory and hard disks. It provides almost capacity-free space for mobile devices over wireless IP networks. However, battery lifetime of the mobile devices is reduced rapidly because of power consumption with continuous use of a WLAN device when multimedia contents are being streamed through the mobile IP storage. This paper proposes an energy-efficient WLAN device power control technique for streaming multimedia contents with the mobile IP storage. The proposed technique consists of a prefetch buffer input/output module, a WLAN device power control module, and a reconfigurable prefetch buffer module. Besides, it adaptively determines the size of the prefetch buffer according to a quality of the multimedia contents, and it dynamically controls the power mode of the WLAN device on the basis of power on-off operations while streaming the multimedia contents. We evaluate the performance of the proposed technique on a PXA270-based mobile device that employs the embedded linux 2.6.11, Intel iSCSI reference codes, and a WLAN device. Extensive experiments reveal that the proposed technique can save the energy consumption of the WLAN device up to 8.5 times with QVGA multimedia contents, as compared with no power control.

A Buffer Architecture based on Dynamic Mapping table for Write Performance of Solid State Disk (동적 사상 테이블 기반의 버퍼구조를 통한 Solid State Disk의 쓰기 성능 향상)

  • Cho, In-Pyo;Ko, So-Hyang;Yang, Hoon-Mo;Park, Gi-Ho;Kim, Shin-Dug
    • The KIPS Transactions:PartA
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    • v.18A no.4
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    • pp.135-142
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    • 2011
  • This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

Scaling down data/index page structure of the NVRAM based DBMS with the small size blocks (소형 블록 DBMS의 데이터/인덱스 페이지 구조 소형화를 통한 NVRAM 성능 개선)

  • Bae, Sang-Hee;Lee, Taehwa;Cha, Jaehyuk
    • Journal of Digital Contents Society
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    • v.14 no.1
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    • pp.15-23
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    • 2013
  • In response to the demands of large-scale data processing with low-power and new application, a storage system using SSD (Solid State Disk/Drive) with fast input-output performance instead of hard disc has appeared as storage device. Studies on methods to overcome specific problems of SSD such as various processing data units, out-place-update and limited delete count have been actively conducted. However, declining performance and stability have not been resolved yet when storing case specific data with small scale that causes frequent random write in hard disc or SSD. This thesis suggests a system structure that stores index requesting frequent random write in NVRAM capable of byte access by using characteristics such as byte unit fast read / write of NVRAM, non-volatile and smaller size of actual changed data size in index page than block size.

An Offline FTL Algorithm to Verify the Endurance of Flash SSD (플래시 SSD의 내구성을 검증하기 위한 FTL 오프라인 알고리즘)

  • Jung, Ho-Young;Lee, Tae-Hwa;Cha, Jae-Hyuk
    • Journal of Digital Contents Society
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    • v.13 no.1
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    • pp.75-81
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    • 2012
  • SSDs(Solid State Drives) have many attractive features such as high performance, low power consumption, shock resistance, and low weight, so they replace HDDs to a certain extent. An SSD has FTL(Flash Translation Layer) which emulate block storage devices like HDDs. A garbage collection, one of major functions of FTL, effects highly on the performance and the lifetime of SSDs. However, there is no de facto standard for new garbage collection algorithms. To solve this problem, we propose trace driven offline optimal algorithms for garbage collection of FTL. The proposed algorithm always guarantees minimal number of erase operation. In addition, we verify our proposed algorithm using TPC trace.

Dependability Analysis Methodology and Tools based on SMART for SSD (SSD를 위한 SMART 기반 신뢰성 분석 방법론 및 도구)

  • Kim, Se-Soog;Lee, Sang-Yup;Jeon, Jeong-Ho;Choi, Jong-Moo;Yang, Joong-Seob;Mo, Yeon-Jin;Shin, Young-Kyun
    • Proceedings of the Korean Information Science Society Conference
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    • 2011.06b
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    • pp.33-36
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    • 2011
  • 본 논문에서는 SMART(Self-Monitoring Analysis and Reporting Technology)를 기반으로 SSD(Solid State Drives) 저장 장치의 신뢰성을 분석할 수 있는 방법론과 도구를 제안한다. 방법론은 SSD를 구성하는 플래시 메모리의 결함 종류, 결함들을 효과적으로 모니터링 할 수 있는 SMART 속성과 임계값, 그리고 이를 기반으로 SSD의 신뢰성을 예측할 수 있는 모델로 구성된다. 이 방법론은 신뢰성 분석 도구로 구현 되었으며, 이 도구는 Workload generator, SMART monitor, Dependability analyzer, 그리고 GUI viewer로 구성된다. 실제 두 회사에서 생산한 6개의 SSD를 이용하여 실험한 결과, SMART를 기반으로 SSD의 고장 예측이 가능하며, 여러 속성들을 동시에 고려하였을 때 예측의 정확도가 높아짐을 발견하였다.

Design and Test Flash-based Storage for Small Earth Observation Satellites (소형 지구 관측 위성용 플래시 기반 저장장치 설계 및 시험)

  • Baek, Inchul;Park, Hyoungsic;Hwang, Kiseon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.13 no.5
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    • pp.253-259
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    • 2018
  • Recently, small satellite industries are rapidly changing. Demand for high performance small satellites is increasing with the expansion of Earth Observation Satellite market. A next-generation small satellites require a higher resolution image storage capacity than before. However, there is a problem that the HW configuration of the existing small satellite image storage device could not meet these requirements. The conventional data storing system uses SDRAM to store image data taken from satellites. When SDRAM is used in small satellite platform of a next generation, there is a problem that the cost of physical space is eight times higher and satellite price is two times higher than NAND Flash. Using the same satellite hardware configuration for next-generation satellites will increase the satellite volume to meet hardware requirements. Additional cost is required for structural design, environmental testing, and satellite launch due to increasing volume. Therefore, in order to construct a low-cost, high-efficiency system. This paper shows a next-generation solid state recorder unit (SSRU) using MRAM and NAND Flash instead of SDRAM. As a result of this research, next generation small satellite retain a storage size and weight and improves the data storage space by 15 times and the storage speed by 4.5 times compare to conventional design. Also reduced energy consumption by 96% compared to SDRAM based storage devices.

Performane Modeling of Flash Memory Storage Systems Using Simulink (시뮬링크를 이용한 플래시메모리 저장장치 성능 모델링)

  • Min, Hang Jun;Park, Jeong Su;Lee, Joo Il;Min, Sang Lyul;Kim, Kanghee
    • IEMEK Journal of Embedded Systems and Applications
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    • v.6 no.5
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    • pp.263-272
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    • 2011
  • The complexity of flash memory based storage systems is high due to diverse host interfaces and other design choices such as mapping granularity, flash memory controller execution models and so on. Thus, it is possible that the actual performance after implementation is not consistent with the target performance. This paper demonstrates that the performance prediction of flash memory based storage systems is possible through performance modeling that takes into account various design parameters. In the performance modeling, the FTL, which is the core element of flash memory based storage systems, is modeled as a set of (copy-on-write) logs and their interactions. Also, the flash memory controller is modeled based on the classification proposed in the design of the Ozone flash controller. In this study, the performance model has been implemented using Simulink and experimental results are presented and analyzed.