• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3028-3030
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• 2005

본 논문에서는 다목적 위성 3호용 탑재 컴퓨터 개발을 위한 DM 설계모델을 기술하였다. 기존의 2호기에서 프로세서 모델이 186에서 386으로 변환 것 이외 모든 내부구조가 비슷하였으나 3호기는 위성의 전체적인 성능을 향상시키기 위하여 프로세서와 내부 인터페이스버스 및 모든 구조를 새로운 설계 개념을 도입하여 국내독자 모델을 개발하고자 한다. 그럼으로 본 논문은 초기 설계모델(DM)의 검토를 통하여 향후 비행 모델개발가능성을 파악하는 근거를 제시하였다.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.6
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• pp.519-524
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• 2007

The OBC(on-board computer) of a satellite which plays a role of the controller for the satellite should be equipped with preventive measures against transient errors caused by SEU(single event upset). Since memory devices are pretty much susceptible to these transient errors, it is essential to protect memory devices against SFU. A common method exploits an error detection and correction code and additional memory devices, combined with periodic memory scrubbing. This paper proposes an effective memory scrubbing scheme for the OBC of STSAT-2. The memory system of the OBC is briefly mentioned and the reliability of the information stored in the memory system is analyzed. The result of the reliability analysis shows that there exist optimal scrubbing periods achieving the maximum reliability for allowed overall scrubbing overhead and they are dependent on the significance of the information stored. These optimal scrubbing periods from a reliability point of view are derived analytically.

• Journal of Satellite, Information and Communications
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• v.5 no.2
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• pp.1-7
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• 2010

For many years the development and verification of on-board flight software have been essentially performed on STB (Software Test Bed) environments which consist of real hardware in KARI. During development of on-board flight software on STB, we experienced many difficulties such as the late delivery of target hardware and limitation to access STB simultaneously by multiple developers. And it takes too much time and cost to build up multiple STBs. In order to successfully resolve this kind of problems, the software-based spacecraft simulator has been developed. The simulator emulates the on-board computer, I/O modules and power controller units and it supports the debugging and test facilities to software engineers for developing flight software. Also the flight software can be loaded without any modification and can be executed as pseudo real-time. This paper presents the architecture and design of software-based spacecraft simulator, and flight software development and verification under this environment.

• Bulletin of the Korean Space Science Society
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• 2003.10a
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• pp.58-58
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• 2003

과학위성 1호의 컴퓨터 시스템은 지상국 명령 및 데이터 처리, 위성 자세 제어, 위성체 운용, 상태 감시, 탑재체 운용, 배터리의 충방전 제어 등을 담당하며, 우리별 3호 위성을 통하여 검증된 컴퓨터 시스템을 기반으로 개발되었다 과학위성 1호의 컴퓨터 시스템은 탑재 컴퓨터(On-board Computer)와 비행 소프트웨어(Flight Software)로 구성된다. 과학위성 1호의 탑재 컴퓨터는 우리별 3호의 탑재 컴퓨터에 비하여 FPGA를 사용함으로써 크기 및 무게의 소형화를 추구하였고, 네트워크 제어기를 내장함으로써 통신 성능의 개선을 이루었다. 그리고 EEPROM을 장착하여 위성 운용 기간 도중에 발생할 수 있는 소프트웨어의 변경에도 대응하였다 과학위성 1호의 비행 소프트웨어는 우리별 3호의 비행 소프트웨어를 기반으로 하여 과학위성 1호의 명령 및 데이터 처리 시스템과 임무에 적합하도록 개발되었다.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.34-36
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• 2020

본 논문은 전기자동차용 탑재형 충전기에 사용되는 능동 전력 디커플링 회로의 커패시턴스 저감 기법을 제안한다. 탑재형 충전기의 허용 DC-link 전압 리플과 커패시턴스 사이의 관계를 분석하고, 허용 리플 크기에 따른 최적 커패시턴스의 크기를 도출한다. 제안하는 설계 기법은 시뮬레이션 및 실험 결과를 기반으로 검증한다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.1
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• pp.98-105
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• 2004

• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.54-60
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• 2013

The need for high performance of on-board computer (OBC) is essential due to the growing requirements and diversified missions, and so OBC has been developed on the basis of the standard design and reconfigurable modularization in order to improve the utilization of OBC for different missions. The processor in OBC of next generation satellite which is currently developed by KARI is adopted the LEON2-FT/AT697F processor based SPARC v8 as main processor and controls various devices such as SpaceWire, MIL-STD-1553B and CAN through PCI on the standardized communication chips. This paper presents the architecture and design of system software for LEON2-FT processor based on PCI, and development of PCI software component. Also it describes the porting of VxWorks 6.5 for LEON2-FT and the test under the simulation environment for LEON2-FT and PCI with communication chips.

• Journal of Satellite, Information and Communications
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• v.11 no.3
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• pp.92-99
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• 2016

AIS(Automatic Identification System) is an vessel traffic management system which exchanges vessel data with other nearby ships, AIS base stations using VHF band. A domestic AIS base station is located along coast lines or island. So it is difficult to collect vessel data from the ocean. To solve this problem, we adopted AIS payload on the low earth orbit satellite. The AIS payload on the satellite is interfaced with OBC(On-Board Computer) via UART and the FSW(Satellite Flight Software) manages it. The FSW have to receive AIS command from ground station and forward to AIS payload. Similarly FSW have to receive response, OBP, OGP data from AIS payload and it is downlink to the ground station. So in this paper we describe the FSW design & implementation for AIS payload.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.9
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• pp.104-112
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• 2005

This paper presents the technique to develop an operational flight program(OFP) of avionic system computer(ASC) which integrates the avionics control, navigation and fire control and provides informations for flight, navigation and weapon aiming missions. For the development of the OFP of ASC, two i960KB chips are used as central processing units board and standard computer interface library(SCIL) which is built in house is used. The Irvine compiler corporation(ICC) integrated development environment(IDE) and the programming language Ada95 are used for the OFP development. We designed the OFP to a computer software configuration item(CSCI) which consists of to three parts for independency of software modules. The OFP has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the OFP such as software integrated test, and ground functional test.

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.460-465
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• 2019

In this study, we aim to derive a solution from the structural analysis for electrical failure of single board computers for computing navigation information. By analyzing the characteristic factor, we identify that crack occur on the central processing unit board due to a certain structural problem, and that the physical effect by the crack make communication function be impossible to perform, which it causes booting error. In order to find the location of excessive stress causing the crack, structural analysis for the single board computer is done. From the structural analysis, the areas where stress concentration occurs are identified, and improvement methods changing the structures are developed. As a result, we shows that stresses are reduced entirely on the stress distribution for the improved structure. In addition, heat analysis shows that changing the structure to reduce stresses is not affect to the heat radiation, and the thermal resistance of the actual equipment is verified by measuring the temperature of the heat sink applied with the improved structure.