• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1033-1036
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• 1998

본 논문은 FLEX 디코더에서 필요한 심볼 클럭을 생성하기 위한 심볼 동기 알고리즘을 제안하고, 제안한 알고리즘을 기본으로 한 심볼을 동기회로의 설계에 관한 것이다. 제안한 알고리즘은 조-만 게이트 동기 (ELGS:Early-Late Gate Synchronization)기법을 이용하고 있다. VHDL(VHSIC Hardware Description Language)로 설계된 심볼 동기회로는 Synopsys 툴을 이용하여 기능레벨의 시뮬레이션을 수행하였고, Altera MAX+plus II를 이용하여 타이밍 분석을 수행하였다. 실험 결과로부터 Source unit와 FLEX 디스코더와의 시스템 동기가 정확히 이루어짐을 확인하였다.

• Journal of KIISE:Information Networking
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• v.35 no.2
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• pp.166-172
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• 2008

This paper proposes an autonomous decentralized frame synchronization system for Ad-hoc Inter-Vehicle Communication Network (IVCN). We have to consider the feature of Ad-hoc IVCN: "time variant" about the number and the location of vehicles and receive power in IVCN, frame timing, and fading. Proposed scheme is different from other decentralized synchronization systems that have association with a fixed base station, and from centralized Personal Communication Systems. This system includes an autonomous decentralized frame synchronization scheme for Ad-hoc IVCN, a high-speed algorithm, a protocol for a newly joining subscriber in IVCN, and a utilization of spread spectrum ranging for frame timing error of the system under highway conditions. Performance evaluation of proposed scheme is validated through simulation. It is shown that Ad-hoc IVCN can be carried out among one and surrounding vehicles in such environment.

• Journal of Energy Engineering
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• v.25 no.2
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• pp.29-36
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• 2016

In this study, diesel/natural gas dual-fuel engine was studied numerically using DoE method. The engine is CI engine for power generation and modelled by 1-D simulation GT-power. The combustion and emission characteristics were analyzed as a function of IVO, IVC and the ratio of natural gas to total fuel enegy. As the proportion of natural gas increases, the BSFC(Brake specific fuel consumption) is increased and BSNOx(Brake specific NOx) is decreased. If specific valve timing to improve the BSFC is applied to the engine, the BSFC is decreased by 1% and simultaneously BSNOx is decreased by 36%.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.202-204
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• 2003

EISC ISA를 기반으로 한 64 비트 고성능 내장형 마이크로프로세서 AE64000의 효과적인 성능 향상을 위해서 비용 대비 성능 향상이 우수한 분기 예측 기법을 도입하여 AE64000 파이프라인에 적합한 분기 예측기를 추가로 설계하고 SPEClnt 벤치마크 및 타 내장형 벤치마크의 성능 분석 시뮬레이션을 통해 최적의 분기 예측기의 구조를 결정하였다. AE64000에서 LERI 명령 처리를 위해 AE64000 파이프라인에 추가된 독특한 IFU에 의하여 복잡성을 갖지만, IF 단계의 PC 대신에 IFU 단계의 PrePC를 이용하여 분기 명령을 명령어 prefetch 단계에서 예측함으로써, 올바른 분기 예측시 분기로 인한 손실을 제거할 수 있다. 결과적으로 최종 선정된 최적의 분기 예측기는 Verilog로 구현하여 AE64000 프로세서 코어 모델과 통합 합성하였고 아울러 추가되는 면적과 최종 목표 클럭에 동작하기 위한 타이밍 분석을 통해 최종 생산에 적합하도록 설계된 분기 예측기의 기능 및 타이밍 검증을 수행하였다. 최종 구현된 분기 예측기는 프로세서 칩 전체의 1% 미만의 비용으로 최고 12%의 성능 향상을 달성하여 성능 대비 면적의 효율성에서 높은 결과를 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.27-33
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• 2000

Gardner’s algorithm is one of the useful algorithm for NDD(Non-Decision Directed) symbol synchronization in PAM communications. But the algorithm has a weak point such as pattern noises increasing in multi-level PAM. To insert a pre-filter in the algorithm is able to reduce timing jitter and pattern noise. In this paper, we analyze statistical properties of NDD algorithm to find an optimal parameter of the pre-filter for improving timing jitter and PLL locking. As a simulation result, optimum value of pre-filter parameter, $\beta$, is 0.3 and 0.5 at the roll off factor of the channel, $\alpha$, is 0.5 and 1.0, respectively. Optimum parameters of the pre-filter for clock synchronization of all-digital 256-QAM demodulator is shown in the results.

• Journal of the Korean Magnetics Society
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• v.20 no.1
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• pp.24-27
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• 2010

This paper presents the design optimization of a linear actuator for fast response of electromagnetic engine valve. The optimization is performed using generic algorithm which is one of global search techniques and not highly dependent on either initial conditions or constraints in the solution domain to maximize the mechanical frequency of the armature mass and valve spring stiffness for fast response of the engine valve. In the results, the mechanical frequency is improved by 30 %.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.583-586
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• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• Journal of the Korean Data and Information Science Society
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• v.22 no.2
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• pp.255-267
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• 2011

The aim of this study is to utilize system trading for making investment decisions and use technical analysis and Dynamic Time Warping (DTW) to determine similar patterns in the frequency of stock data and ascertain the optimal timing for trade. The study will examine some of the most common patterns in the futures market and use DTW in terms of their frequency (10, 30, 60 minutes, and daily) to discover similar patterns. The recognized similar patterns were verified by executing trade simulation after applying specific strategies to the technical indicators. The most profitable strategies among the set of strategies applied to common patterns were again applied to the similar patterns and the results from DTW pattern recognition were examined. The outcome produced useful information on determining the optimal timing for trade by using DTW pattern recognition through system trading, and by applying distinct strategies depending on data frequency.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1021-1030
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• 2010

In the sensor network, many tiny nodes construct Ad-Hoc network using wireless interface. As this type of system consists of thousands of nodes, managing each sensor node in real world after deploying them is very difficult. In order to install the sensor network successfully, it is necessary to verify its software using a simulator beforehand. In fact Sensor network simulators require high fidelity and timing accuracy to be used as a design, implementation, and evaluation tool of wireless sensor networks. Cycle-accurate, instruction-level simulation is the known solution for those purposes. In this paper, we developed an instruction-level sensor network simulator for Telos sensor node as named TeloSlM. It consists of MSP430 and CC2420. Recently, Telos is the most popular mote because MSP430 can consume the minimum energy in recent motes and CC2420 can support Zigbee. So that TeloSlM can provide the easy way for the developers to verify software. It is cycle-accurate in instruction-level simulator that is indispensable for OS and the specific functions and can simulate scalable sensor network at the same time. In addition, TeloSlM provides the GUI Tool to show result easily.

• Proceedings of the Korea Information Assurance Society Conference
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• 2004.05a
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• pp.59-64
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• 2004

In this paper a design and an implementation of a crypto chip which implements SEED and Triple-DES algorithms are described. We designed it by VHDL(VHSIC Hardware Description Language) which is a designed system-description language. To apply the chip to various application, four operating Modes such as ECB, CBC, CFB, and CFB are supported. The chip was designed by the Virtex-E XCV2000E BG560 of Xilinx and we confirmed result of it at the FPGA implementation by functional and timing simulation using the Xilinx Foundation Series 3.li.