• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.34-43
• /
• 2008

An OpenLDI receiver circuit for flat-panel display systems was designed and fabricated using $1.8-{\mu}m$ high-voltage CMOS technology. Designed circuit roughly consists of DLL circuit and parallelizers, which recovers clock and parallelize data bits, respectably. It has one clock input and four data inputs. Measurement results showed that it successfully recovers clock signal from input whose frequency is $10Mhz{\sim}65Mhz$, which corresponds data rate of $70Mbps{\sim}455Mbps$ per channel, or $280Mbps{\sim}1.82Gbps$ when all of the four data channels were utilized. A commercial LCD monitor was modified into a test-bench and used for video data transmission at clock frequency of 49Mhz. In the experiment, power consumption was 19mW for core block and 82.5mW for output buffer.

• Journal of Korea Multimedia Society
• /
• v.12 no.3
• /
• pp.329-334
• /
• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.6
• /
• pp.1346-1355
• /
• 2005

Recently, the development of passive optical networks (PON) for FTTH (Fiber-To-The-Home) have been actively conducted. In PON, a burst-mode transceiver is one of key modules. In this paper, we have made the protype module of a 155.52 Mpbs optical burst-mode transceiver with commercially available chips and then have measured the performance. Also, a new method of burst-mode clock recovery have been proposed. The burst-mode clock recovery implemented by using CPLD(Complex Programmable Logic Device) has coupled with the above burst-mode transceiver and has been tasted.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2002.11a
• /
• pp.291-294
• /
• 2002

본 논문에서는 디지털 TV 데이터 방송에 있어 핫스팟 기능을 지원하기 위한 비트스트림 제작에 관하여 서술한다. 디지털 TV 데이터 방송에 있어 핫스팟이란 시청자의 선택에 의해 더 많은 정보를 제공할 수 있는 "클릭 가능한 비디오 객체"를 의미한다. 이 기능은 다른 용도로도 사용될 수 있으나, 특히 TV 전자상거래(T-commerce)에 유용하게 사용할 수 있다. 이러한 기능을 제공하기 위해서는 핫스팟 기능을 처리할 자바 응용프로그램, 즉 엑슬릿(Xlet)과 화면상에서 핫스팟의 시공간적 위치를 지정하는 핫스팟 데이터, 그리고 핫스팟과 주 프로그램화면 간의 동기화를 위한 시간 기준 등이 송출되는 비트스트림 내에서 제공되어야 한다. 본 논문에서는 핫스팟 적용 시나리오를 설명하고 이 시나리오에 따라 핫스팟 기능을 제공할 수 있는 비트스트림을 제작하였다. 보다 더 구체적으로는, 엑슬릿을 ISO/IEC 13818-6 DSM-CC 확장 표준의 오브젝트 캐루젤로, 그리고 핫스팟 데이터를 MPEG-2 프라이벳 섹션(Private section)으로 구성하여 비트스트림에 포함시켰다. 또한, 시간 기준을 위해 DSM-CC 확장 표준에서 규정하고 있는 정규 재생시간(normal play time, NPT) 클록을 이용하여 시간 참조 값을 생성하였으며, 트리거(trigger)를 보내기 위한 이벤트들도 동일 표준에서 규정하고 있는 이벤트 서술자에 따라 생성하여 비트스트림 내에 포함시켰다. 내에 포함시켰다.