• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1991.10a
• /
• pp.390-393
• /
• 1991

• Proceedings of the KIEE Conference
• /
• 1983.07a
• /
• pp.110-112
• /
• 1983

• The Journal of the Korea institute of electronic communication sciences
• /
• v.3 no.3
• /
• pp.177-182
• /
• 2008

Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

• Journal of the Korea Society of Computer and Information
• /
• v.12 no.1 s.45
• /
• pp.155-160
• /
• 2007

Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc.. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.12B
• /
• pp.1506-1513
• /
• 2009

This paper presents a synchronization method to determine the exact demodulation time using the MFM Flag of the 18000-3 PJM mode, along with the hardware structure to implement the proposed method. The proposed system detects an incipient peak using ITS(Initial Time Selector) and a correlator and achieves the final synchronization via identifying the peak position from the comparison of the outputs of two followed additional correlators. The peak detection algorithm and the choice of the templates of the correlators are described. Simulation results show that the proposed system performs successfully in noisy environment.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.6
• /
• pp.2713-2717
• /
• 2011

To transmit data from straggling sensors in water-processing basic industries etc., used Binary-CDMA system has safety voluntarily. But Binary-CDMA is necessity that react very sensitively in environment change as defense about hacking and cracking of various way that change suddenly. Therefore, this paper is that see added cryptographic algorithm for safety and easy update on correlator that a bottle-neck phenomenon is happened in Binary-CDMA to solve problem that is such. Added cryptographic algorithm does to communicate safe information in channel that is not safe as that achieve 1:1 confrontation for sensors by symmetric cryptographic algorithm.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.787-790
• /
• 2003

This paper describes a high speed correlator that can acquire synchronization quickly. The existing addition algorithm is a binary adder tree architecture that will result in extremely slow speed of operation due to many levels of logic required for computation of correlation[2][3]. This paper suggests the new various architectures, which are systolic array architecture, simple pipeline architecture and block systolic array architecture[4][5]. The acquisition performance of the proposed architectures is analyzed and compared with the existing architecture. The comparison results show that the systolic array architecture and the block systolic array architecture reduce the timing delay up to 73% and 31%, respectively. And the results show that the simple pipeline architecture reduces the timing delay up to 53%..

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2003.11a
• /
• pp.198-202
• /
• 2003

An engineer prefers DIFM receiver which is superior to instantaneous response rather than superheterodyne receiver which has a scan rate in normal wide band receiver designing. But DIFM receiver has weak point in sensitivity and continuous wave signal because of special environments. In this paper we propose the method which is certificated through simulation and prototype testing to improve sensitivity of DIFM receiver. And we analyze the important factors of DIFM receiver from our results.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.3
• /
• pp.587-594
• /
• 2010

In this paper, we propose an asynchronous IR-UWB ranging system based on the two-way ranging protocol. The periodic pulse sequence is used to measure a distance between two devices. At the receiver, a received signal is first transformed into a frequency-domain signal using an analog correlator bank and digital signal processing is followed in the frequency-domain. This make it possible for the system to use an ADC with a conversion speed of pulse rate. The proposed algorithm at the receiver side includes a peak detection procedure using mutipath channel compensation and matched filtering, and retransmits a pulse sequence synchronized with the detected peak. The validity of the proposed algorithm is verified from simulation results where the CM1 channel is assumed.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.2
• /
• pp.147-151
• /
• 2009

A wideband correlator, with 45% relative bandwidth is proposed at the frequency range of 3.1-5.1GHz. The structures of the correlator components such as the delay line and the Wilkinson power divider are designed to be realized in transmission line form using the Agilent's Advanced Design System (ADS). The correlator made by using three unique wideband 3-dB couplers, rat-race coupler and one 3-dB wilkinson power divider to reach the required bandwidth. The insertion loss, amplitude imbalance and phase imbalance between ports are presented. The proposed correlator makes compact size better than correlator of conventional structure.