• Journal of the Korea Society of Computer and Information
• /
• v.11 no.6 s.44
• /
• pp.19-26
• /
• 2006

Redundant expressions must be eliminated in order to apply optimization for expressions in SSA Form from CTOC. This paper applied VN(Value Numbering) for this purpose. In order to carry out VN, SSAGraph must be first generated to maintain the information in the SSA Form, equivalent nodes must be found and SCC(Strongly Connected Component) generated. Equivalent nodes are assigned with an identical valnum through SCC. We could confirm elimiations for many nodes that added at SSA Form process after VN. The valnum can be applied in optimization and type inference.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.2
• /
• pp.264-276
• /
• 1995

In this paper, a technique for eliminating conditional branches in the compilers for superscalar processors is presented. The technique consists of three major steps. The first step transforms conditional branches into equivalent expressions using algebraic laws. The second step searches all possible instruction sequences for those expressions using GSO of Granlund/Kenner. Finally an optimal sequence that has the least dynamic count for the target superscalar processor is selected from the GSO output. Experiment result shows that for each conditional branch is the input program matched by one of the optimization patterns, the proposed technique outperforms more than 25% speedup of execution time over the original code when the GNU C compiler and the SuperSPARC processor are used.

• KIPS Transactions on Software and Data Engineering
• /
• v.5 no.5
• /
• pp.209-220
• /
• 2016

While the services of mobile devices like smart phone, tablet, and smart watch have been increased and varied, the software embedded into such devices has been also increased in size and functional complexity. Therefore, increasing operation time of mobile devices for serviceability became an important issue due to the limitation of battery power. Recent studies focus on the software development having efficient behavioral patterns because the energy consumption of mobile devices is caused by software behaviors which control the hardware operations. However, it is often difficult to develop the embedded software with considering energy-efficiency and behavior optimization due to the short development cycle of the mobile services in many cases. Therefore, this paper proposes the refactoring techniques for reducing energy consumption, and enables to fulfill the energy requirements during software development and maintenance. We defined energy bad smells with the code patterns that can excessively consume the energy, and our refactoring techniques are to remove these bad smells. We performed some case studies to verify the usefulness of our refactoring techniques.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.5
• /
• pp.970-976
• /
• 2001

In this paper, OUIG IDL CFE, provided by Sunsoft, is used to take a IDL definitions as inputs and parse those. OmniORB3 is introduced to support functionality of the ORB. Suns CFE produce AST after parsing inputs. Actually, the node of AST Is instances of classes which are derived from CFE classes. As the compiler back end visit the node of the AST using iterator class, UTL_ScopeActiveIterator, it dumps codes of output. During processing, two files are generated. Routines of generating code are invoked by BE_produce.cc and codes are produced while visiting root of AST, idl_global->root(). The dump* functions which dump codes is called according to the type of node. In this paper, Mapping C++ of IDL definition is experimented and results In the same as that of omniidl which is provided by omniORB3. The code of results behavior correctly on omniORB3. In the future, we are interested in optimizing the performance of marshalling code via IDL compiler.

• Journal of Satellite, Information and Communications
• /
• v.12 no.1
• /
• pp.1-5
• /
• 2017

In this paper, multiuser detector (MUD) based on radial basis function (RBF) is proposed and simulated for a multicode direct sequence/code division multiple access (DS/CDMA) system in a multipath fading channel. The performance of RBF-based MUD is compared with that of many suboptimal multiuser detectors in terms of bit error probability. From the simulation results, it is confirmed that the RBF-based MUD outperforms decorrelating detector, and achieves near-optimum performance under various environments. The results in this paper can be applied to design of MUD for a multicode DS/CDMA system.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.3
• /
• pp.149-155
• /
• 2007

In this paper, we propose an real-time implementation of JPEG2000 codec on the ARM9 processor. The implemented codec is designed to separate control codes from data management codes in order to use effectively the system resources such as processor and memory. Especially, in embedded situations like cellular phones it is very important to provide good services using limited processor and internal memory. Since ARM9 series processors do not provide floating-point, large amount of computational time is required to perform the operation which needs highly repetitive floating-point computations like DWT(discrete wavelet transform). The proposed codec was programed using fixed-point to overcome this weakness. Also code optimization considering cache memory was applied to further improve the computational speed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.4
• /
• pp.646-652
• /
• 2015

In this paper, the system-level performance is evaluated for the feedback scheme on the pre-coding matrix index (PMI) and channel quality indication (CQI), which are required for user selection in the multi-user MIMO system. Our analysis demonstrates that the number of users, the number of selected users, and codebook size are the key factors that govern the performance of the best companion grouping (BCG)-based user scheduling. Accordingly, we have confirmed that the probability of forming the co-scheduled user group is determined by these factors, which implies that the number of PMI's and codebook size can be dynamically determined so as to maximize the average system throughput as the number of users varies in the cell.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1997.11a
• /
• pp.151-156
• /
• 1997

본 논문은 저비용이면서 정확한 제어를 수행하는 새로운 퍼지 제어기의 VHDL 설계 및 FPGA 구현을 자동적으로 수행하는 통합 개발 환경(IDE : Integrated Development Environment)을 다룬다. 이를 위해 FLC의 자동 설계 및 구현의 전 과정을 하나의 환경 내에서 개발 가능하게 하는 퍼지 제어기 자동 설계 및 구현 시스템 (FLC Automatic Design and Implementation Station :FADIS)을 개발하였는데 이 시스템은 다음 기능을 포함한다. (1) 원하는 퍼지 제어기의 설계 파라메터를 입력받아 이로부터 FLC를 구성하는 각 모듈의 VHDL 코드를 자동적으로 생성한다. (2) 생성된 각 모듈의 VHDL 코드가 원하는 동작을 수행하는지를 Synopsys사의 VHDL Simulator상에서 시뮬레이션을 수행한다. (3) Synopsys사의 FPGA Compiler에 의해 VHDL 코드를 합성하여 FLC의 각 구성 모듈을 얻는다. (4) 합성된 모듈은 Xilinx사의 XactSTep 6.0에 의해 최적화 및 배치, 배선이 이루어진다. (5) 얻어진 Xilinx rawbit 파일은 VCC사의 r2h에 의해 C 언어의 header 파일 형태의 하드웨어 object로 변환된다. (6) 하드웨어 object를 포함하는 응용 제어 프로그램의 실행 파일을 재구성 \ulcorner 능한 FPGA 시스템 상에 다운로드한다. (7) 구현된 FLC의 동작 과정은 구현된 FLC와 제어 target 사이의 상호 통신에 의해 모니터링한다. 트럭 후진 주차 제어에 사용하는 퍼지 제어기 설계 및 구현의 전 과정을 FADIS상에서 수행하여 FADIS가 완전하게 동작하는지를 확인하였다.

• Journal of Software Assessment and Valuation
• /
• v.15 no.1
• /
• pp.43-53
• /
• 2019

BigCloneBench has recently been used for performance evaluation of code clone detection tool using machine learning. However, since BigCloneBench is not a benchmark that is optimized for machine learning, incorrect learning data can be created. In this paper, we have shown through experiments using machine learning that the set of Type-4 clone methods provided by BigCloneBench can additionally be found. Experimental results using Tree-Based Convolutional Neural Network show that our proposed method is effective in improving BigCloneBench's dataset.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.8
• /
• pp.1149-1154
• /
• 2013

In this paper, an algorithm having new edge growth with depth constraints for constructing Tanner graph of LDPC(Low density parity check) codes is proposed. This algorithm reduces effectively the number of small stoping set in the graph and has lower complexity than other algorithm. The simulation results shows the improved performance of the LDPC codes constructed by this algorithm.