• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2329-2331
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• 2004

본 논문에서는 이동 로봇의 경로 추종 제어를 위해 웨이블릿 신경 회로망에 기반한 예측 제어기의 설계 방법을 제안하고자 한다. 제안한 방법에 의해 설계된 제어기는 이동 로봇의 동특성을 예측하기 위한 웨이블릿 신경회로망 기반 예측기와 예측 제어기로 구성된다. 제안한 방법에서 모델링 및 제어기로 적용되는 신경 회로망의 장점과 우수한 해석 능력을 가진 웨이블릿 변환의 장점을 결합한 웨이블릿 신경 회로망을 이용하여 이동 로븟의 동특성을 모델링하여 예측 제어기에서의 비용 함수 최소화에 적용한다. 경로 추종 제어의 목적인 이동 로봇의 실제 출력과 예측기의 출력 오차를 최소화하기 위해 웨이블릿 신경 회로망의 파라미터 동정 및 예측 제어기는 경사 하강법을 이용하여 학습한다. 마지막으로 컴퓨터 모의 실험을 통하여 제안한 예측 제어 시스템의 적용가능성 및 효율성을 검증하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1090-1098
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• 1999

In this paper ERP-4 viterbi decoder for magnetic disk read channel is designed. The viterbi decoder consists of ACS circuit, path memory circuit, minimum detection circuit, and output selection circuit. In the viterbi decoder the number of state is reduced from 8 to 6 using (1,7) RLL codes and modulo comparison based on 2's complement arithmetic is applied to handle overflow problem of ACS module. Also to determine the correct symbol values in nonconvergent condition of path memory, pipelined minimum detector which determines path with minimum state metric is used. The EPR-4 viterbi decoder is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology and consists of about 15,300 transistors and has 250 Mbps data rates under 3.3 volts.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1641-1642
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• 2006

본 연구에서는 NDIR(non dispersive infrared absorption) 가스센서의 소형화와 저가화를 목표로 2개의 오목 거울을 이용한 새로운 광 공동(optical cavity) 구조를 제안하고, 구조에 따른 광 출력 특성을 시뮬레이션하였다. Optical cavity는 광 경로증가 및 광 집속 구조로 설계하고, 각각의 출력단에서 검출되는 광 출력을 시뮬레이션한 결과 광 집속 구조의 팡 출력이 더 효율적임을 확인하였다. 집광구조에서의 광 출력을 최대로 하기 위해 광의 초점을 찾아보았다. 집광 구조를 사용하지 않는 단순 평행 광이 조사되는 경우, 적외선 센서부에 입사되는 광 출력은 최대 0.024W이다. 그러나 집광구조에서는 optical cavity의 광축에서 센서의 위치를 $15\sim20mm$까지 변화시켜 시뮬레이션한 결과 거리 18.83mm 일 때 조사되는 광 출력이 약 0.153W로 약 7배 증가됨을 확인하였다.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.79-88
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• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• Korean Journal of Optics and Photonics
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• v.10 no.1
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• pp.53-57
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• 1999

We established the laser oscillator using Nd:YAG crystal grown at Ssang Yong company in Korea and investigated the characteristics of oscillation, Q-switching and wave front of output beam. We measured the single pass gain by controlling the threshold input energy with two output couplers of different output reflectances. Moreover, we compared the gain measured by different output couplers with the gain directly measured by the laser amplifier. The peak power of Q-switching, the pulse width, and the single pass gain coefficient at the threshold energy were 1.5 MW, 30ns, and 0.0958 cm-$^1$ respectively and they were compared with those of the commercial Nd:YAG crystal. Our crystal was proved to be as good as the commercial crystal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.282-287
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• 2003

A network is made up of interconnected switching units. The role of a switching unit is to set up a connection between and input port and an output, according to the routing information. But then the most switching network use Banyan switch, their occurs the internal blocking , which attempts to use the same link two cells. This paper proposed and designed for a improvement Batch-Banyan network which can routed two path assignment between its input ports and output ports without only blocking. The network is constructed of two sorting blocks ($4{\times}4$), one switch network($8{\times}8$) block. As a result, the switch network performance increased 4% reduced to half of the hardware complexity of sorting boxes when compare the new switching system with Batcher-Banyan network system.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2204-2212
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• 1999

In this paper, we present techniques which perform incremental timing analysis using Timed Boolean Algebra that solves the false path problem and extracts the timing information in combinational circuits. Our algorithm sets histories of internal inputs that are substituted for internal output and extracts maximal delays through checking sensitizability of primary outputs. Once finding the sum of primitive delay terms, then it applies modified delay with referencing histories of primary output and it can extract maximal delays of primary outputs fast and efficiently. When the structure of circuit is changed, there is no need to compute the whole circuit again. We can process partial timing analysis of computing on the gates that are need to compute again. These incremental timing analysis methods are considered both delay changes and structure of circuit, and can reduce the costs of a trial error in the circuit design.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.2
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• pp.71-78
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• 2017

In This Paper, A DC-DC Boost Converter for Portable Device has been Proposed. The Converter Which is Operated with 1 MHz High Switching Frequency is Capable of Reducing Mounting Area of Passive Devices Such as Inductor and Capacitor, Consequently is Suitable for Portable Device. This Boost Converter Consists of a Power Stage and a Control Block and a Protect Block. Proposed DC-DC Boost Converter has been Designed a 0.18 um Magnachip CMOS Process Technology, we Examined Performances of the Fabricated Chip and Compared its Measured Results with SPICE Simulation Data. Simulation Results Show that the Output Voltage is 4.8 V in 3.3 V Input Voltage, Output Current 95 mA Which is Larger than 20~50 mA.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.102-103
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• 2013

화석 연료의 고갈과 유가 급등으로 인해 자동차 업체에서는 친환경 차량 개발에 힘쓰고 있다. FCEV는 차량 구동용 전동기에 필요한 에너지를 연료전지를 통해 공급받게 된다. 하지만 연료전지의 특성상 연료전지와 배터리를 같이 사용하게 된다. 본 논문에서는 일반적인 Half-bridge 타입의 양방향 컨버터에 스위치를 추가하여 양방향 buck, boost가 가능한 컨버터를 설계하였다. 전동기 구동용 인버터는 전압형 인버터가 사용되는데 전압형 인버터에서 발생하는 출력은 데드타임과 스위칭 소자의 전압 강하에 의해 왜곡된 전압과 전류를 출력하게 되고 이러한 출력은 토크와 속도에 나쁜 영향을 끼치게 된다. 이러한 문제를 해결하기 위해 전동기의 속도에 따라 DC-link 전압을 가변하여 공급한다.

• Journal of Advanced Navigation Technology
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• v.26 no.6
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• pp.487-495
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• 2022

This paper describes the design and development of a high-power transmit receive module(TRM) for mounting on X-band synthetic aperture radar(SAR) of the NEXTSat-2. The TRM generates a high-power pulse signal with a bandwidth of 100 MHz in the target frequency range of X-band and amplifies a low-noise on the received signal. Tx. path of the TRM has output signal level of more than 200 watts (53.01 dB), pulse droop of 0.35 dB, signal strength change of 0.04 dB during transmission signal output, and phase change of 1.7 ˚. Rx. path has noise figure of 3.99 dB and gain of 37.38 ~ 37.46 dB. It was confirmed the TRM satisfies all requirements. The TRM mounted on the NEXTSat-2 flight model(FM) which will be launched using the KSLV-II (Nuri).