• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.184-186
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• 2004

검사점 작성을 이용하는 실시간 태스크의 스케줄링 가능성을 알기 위한 선행 조건으로 최악 수행시간을 분석하고 이를 최소로 하는 효율적인 검사점 작성의 위치를 결정하는 방법을 제시한다. 여기서 사용하는 조건은 k 개의 연속적인 결함을 허용하고 태스크의 검사점 작성 비용이 고정적인 경우와 가변적인 경우를 가정한다. 이러한 각 조건에서 최악 수행 시간을 최소로 하는 검사점 작성 알고리즘을 제시한다.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.21-23
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• 1999

CPU에게 최상위 우선순위가 할당된 고정 우선순위 버스 프로토콜에서는 CPU와 DMA 컨트롤러의 버스 요구가 충돌할 경우 DMA 전송이 지연된다. 본 논문에서는 CPU와 다수의 DMA 컨트롤러가 시스템 버스를 공유하는 환경에서 DAM I/O 요구의 최악 응답시간을 분석하는 기법을 제안한다. 제안하는 최악 응답시간 분석 기법은 다음의 세단계로 구성되어 있다. 첫 번째 단계에서는 CPU 상에서 수행중인 각 CPU 태스크별로 최악 버스 요구 패턴을 구한다. 두 번째 단계에서는 이들 CPU 태스크의 최악 버스 요구 패턴을 모두 통합해 CPU 전체의 최악 버스 요구 패턴을 구한다. 최종 세 번째 단계에서는 CPU의 최악 버스 요구 패턴으로부터 DMA 컨트롤러의 버스 가용량을 구하고 DMA I/O 요구의 최악 응답시간을 산출한다. 모의 실험을 통해 제안하는 분석 기법일 일반적인 DMA전송량에 대해 20% 오차 범위 이내에서 안전한 응답시간을 산출함을 보였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.576-578
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• 2007

본 논문에서는 Ingo Molnar 의 realtime-preempt 패치가 적용된 리눅스를 활용한 실시간 시스템에서 다른 프로세스와 동시에 수행하지 않고도 다른 프로세스에 의한 실시간 프로세스의 최악 응답시간의 변화를 예측할 수 있도록 최악 응답 시간에 영향을 주는 커널 모드에서 선점 금지 시간을 프로세스 별로 분석을 하기 위한 도구를 커널 모듈로 구현하여 실시간 프로세스의 최악 응답 시간을 예측할 수 있음을 보였다.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.148-159
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• 2005

We propose a technique for finding the worst case response time (WCRT) of a DMA request that is needed in the schedulability analysis of a whole real-time system. The technique consists of three steps. In the first step, we find the worst case bus usage pattern of each CPU task. Then in the second step, we combine the worst case bus usage pattern of CPU tasks to construct the worst case bus usage pattern of the CPU. This second step considers not only the bus requests made by CPU tasks individually but also those due to preemptions among the CPU tasks. finally, in the third step, we use the worst case bus usage pattern of the CPU to derive the WCRT of DMA requests assuming the fixed-priority bus arbitration protocol. Experimental results show that overestimation of the DMA response time by the proposed technique is within $20\%$ for most DMA request sizes and that the percentage overestimation decreases as the DMA request size increases.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.365-374
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• 2005

Schedulability analysis is necessary to build reliable embedded real-time systems. For schedulability analysis, worst-case execution time(WCET) analysis that computes upper bounds of the execution times of tasks, is required indispensably. WCET analysis is done in two phases. The first phase is high-level analysis that analyzes control flow and finds longest paths of the program. The second phase is low-level analysis that computes execution cycles of basic blocks taking into account the hardware architecture. In this thesis, we design and implement integrated WCET analysis tools. We develop the WCET analysis tools for XScale-based system called WATER(WCET Analysis Tool for Embedded Real-time system). WATER consist of high-level flow analyzer and low-level execution time analyzer. Also, We compare real measurement for execution of program with analysis result calculated by WATER.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.271-281
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• 2007

Real-time support of embedded OS is not optional, but essential in contemporary embedded systems. In order to achieve these system#s real-time property, it is crucial that schedulability analysis for tasks having its property have been accomplished before system execution. Acquiring Worst-Case Execution Time(WCET) of task is a core part of schedulability analysis. Because traditional WCET tools analyze only its estimation of application task(i.e. program), it is not considered that application tasks are affected by scheduling primitives(e.g. scheduler, interrupt service routine, etc.) of OS when it schedules them. In this paper, we design and implement WCET analysis tool which deliberates on scheduling primitives of system using embedded Linux widely used in embedded OSes. This tool can estimate either WCET of normal application programs or corresponding primitives which have an influence on schduling property in embedded Linux kernel. Therefore, precision of estimation about schedulability analysis is improved. We develop this tool as Eclipse#s plug-in to work properly in any platform and support convenient interface or functionality for user.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.445-450
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• 2007

NAND 플래시 메모리 기반의 실시간 임베디드 시스템에서는 일반적으로 shadowing 기법을 통해 프로그램을 수행한다. 그러나 shadowing 기법은 시스템의 부팅 시간을 증가시키고 불필요한 DRAM 영역을 차지한다는 단점 때문에 자원 제약이 심한 실시간 임베디드 시스템에는 적합하지 않다. 이에 대한 대안 중 하나는 demand paging 기법을 활용하는 것이다. 단, demand paging 환경에서는 page fault에 의한 시간 지연 때문에 태스크의 최악 실행 성능을 예측하기 어렵다. 따라서 본 논문에서는 NAND 플래시 메모리 기반의 실시간 임베디드 시스템에서 demand paging 비용을 고려한 태스크 최악 성능 분석 기법을 제안한다. 제안하는 기법은 각 태스크에 대해 demand paging 비용을 계산하고, 이를 전통적인 WCRT 분석 기법과 결합하는 방법을 사용한다. 또한 demand paging 비용과 WCET 분석을 독립적으로 고려함으로써, 최악의 경우에도 분석 결과의 안정성을 보장하고 기존의 방법에 비해 분석 복잡도를 줄였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.866-874
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• 2006

This paper proposes a new Dynamic Voltage Scaling(DVS) algorithm to achieve low-power scheduling of aperiodic hard real-time tasks. Aperiodic tasks schedulingcannot be applied to the conventional DVS algorithm and result in consuming energy more than periodic tasks because they have no period, non predictable worst case execution time, and release time. In this paper, we defined Virtual Periodic Task Set(VTS) which has constant period and worst case execution time, and released aperiodic tasks are assigned to this VTS. The period and worst case execution time of the virtual task can be obtained by calculating task utilization rate of both periodic and aperiodic tasks. The proposed DVS algorithm scales the frequency of both periodic and aperiodic tasks in VTS. Simulation results show that the energy consumption of the proposed algorithm is reduced by 11% over the conventional DVS algorithm for only periodic task.

• Journal of the Korea Society of Computer and Information
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• v.11 no.6 s.44
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• pp.113-123
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• 2006

Flash memory has been increasingly used in handhold devices not only for data storage, but also for code storage. Because NAND flash memory only provides sequential access feature, a traditionally accepted solution to execute the program from NAND flash memory is shadowing. But, shadowing has significant drawbacks increasing a booting time of the system and consuming severe DRAM space. Demand paging has obtained significant attention for program execution from NAND flash memory. But. one of the issues is that there has been no effort to bound demand paging cost in flash memory and to analyze the worst case performance of demand paging. For the worst case timing analysis of programs running from NAND flash memory. the worst case demand paging costs should be estimated. In this paper, we propose two different WCRT analysis methods considering demand paging costs, DP-Pessimistic and DP-Accurate, depending on the accuracy and the complexity of analysis. Also, we compare the accuracy butween DP-Pessimistic and DP-Accurate by using the simulation.

• Transactions of the Korean Society of Automotive Engineers
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• v.10 no.5
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• pp.114-120
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• 2002

In a distributed real-time control system, it is essential to confirm the timing behavior of all tasks because these tasks of each real-time controller have to finish their processes within the specified time intervals called a deadline. In order to satisfy this objective, the timing analysis of a distributed real-time system such as shcedulability test must be performed during the system design phase. In this study, a simple application of CAN fur a vehicle body network system is formulated to apply to a holistic scheduling analysis, and the worst-case execution time (WCET) and the worst-case end-to-end response time (WCRT) are evaluated in the point of holistic system view.