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Implementation of the Digital Current Control System for an Induction Motor Using FPGA (FPGA를 이용한 유도 전동기의 디지털 전류 제어 시스템 구현)

  • Yang, Oh
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.11
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    • pp.21-30
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    • 1998
  • In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

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Design and Implementation of High Sensitivity Single Power Factor Meter. (고감도 단상력률계의 설계 및 시작)

  • 박정후
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.15 no.2
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    • pp.55-60
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    • 1979
  • The forming and design method of single power factor meter is suggested and the sensitive phase angle detect circuit of current and voltage of load was dealt with. In this paper, in order to control and detect of phase angle of the current and voltage, operational amplifier comparator circuit and R-C phase shift circuit was used, and to detect the controlled voltage wave form, the transister chopper pair circuit was used. The test result of this power factor meter was good and reliable at the full range of power factor.

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연소 안정성 평가 시험을 통한 배플 길이의 안정성 여분 평가

  • Kim, Hong-Jip;Lee, Kwang-Jin;Seo, Seong-Hyeon;Kim, Seung-Han;Han, Yeoung-Min;Seol, Woo-Seok
    • Aerospace Engineering and Technology
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    • v.3 no.1
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    • pp.188-196
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    • 2004
  • To optimize and limit the axial length of baffle in KSR-III engine, stability rating tests using pulse gun as one of artificial disturbance devices have been done. Decay time and other parameters for the evaluation of stabilization ability of engine to external perturbation have been analyzed to quantify stabilization capacity of engine, in other words, dynamic stability margin. If baffle does not cover flame zone enough which can be considered as collision region of injector, it wasn't be able to suppress external perturbation sufficiently. The limit of combustion stability margin of engine is assumed to be 50 mm length baffle.

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The Low Cycle Fatigue Behavior of Laser Welded Sheet Metal for Different Materials (이종재료 레이저 용접 판재의 저주기 피로 특성)

  • Kim Seog-Hwan;Kwak Dai-Soon;Kim Woong-Chan;Oh Taek-Yul
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2005.10a
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    • pp.627-631
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    • 2005
  • In this study, low fatigue behavior of laser welded sheet metal were investigated. Before welding, the cross section of butt joint was prepared only by fine shearing without milling process. Specimens were same sheet metal and welding condition that using automobile manufacturing company at present. Butt joint of cold rolled sheet metal was welded by $CO_2$ laser. It is used that welding condition such as laser welding speed was 5.5m/sec and laser output power was 5kW for 0.8mm and 1.2mm sheet metal. The laser weldments were machined same or different thickness and same or different material. In order to mechanical properties of around welding zone, hardness test was performed. Hardness of welding bead is about 2 times greater than base material. We performed the low cycle fatigue tests for obtaining fatigue properties about thickness and the weld line direction of specimen. The results of strain controlled low cycle fatigue test indicate that all specimens occur cyclic softening, as indicated by the decrease in stress to reach a prescribed strain.

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A Development of A Gas Mechanical Pulsator (압력 섭동 장치 설계/제작 및 검증시험)

  • Kim, Tae-Woan;Hwang, Oh-Sik;Ko, Young-Sung;Jung, Se-Yong
    • Journal of the Korean Society of Propulsion Engineers
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    • v.13 no.3
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    • pp.50-57
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    • 2009
  • A gas mechanical pulsator is developed for the study of combustion instabilities in various combustors such as LRE combustor. First, it shows that the mass flow rates and the perturbation frequencies can be successively controlled by the inlet pressure and the rotating speed of a rotating disk with many holes. Second, the device is used as an acoustic amplification source as a substitute for the speaker in the previous acoustic tests and its results show almost the same resonant frequency and damping characteristics compared with the previous results. In conclusion, the result shows that it can be used as a substitute for a speaker in the studies of LRE combustion instabilities, which has a flow and no limitation of amplification, and a device for making a perturbation source in gas flow.

A Design of Predistorter for Controlling the Amplitude of Low-Frequency IM Signals (저주파 혼변조 신호의 크기 조절에 의한 전치 왜곡 선형화기 설계)

  • Jang Mi-Ae;Kim Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.1 s.104
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    • pp.45-51
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    • 2006
  • In this paper, a new predistortion linearizer for controlling the amplitude of low frequency intermodulation distortion signals is proposed. The low frequency intermodulation distortion(IMD) components are generated by harmonic generator. A vector modulator, modulate fundamental signal with low frequency IMD signals, generates predistortion IMD signals and controls amplitude and phase of them with modulation factors. As a result, this predistorter is suppressed IMD signals of power amplifier effectively. The predistortion linearizer has been manufactured to operate in cellular base-station transmitting band($869{\sim}894\;MHz$). The experimental results show that IMD3 of power amplifier are improved more than 20 dB for CW two-tone signals. Also, it's improved the adjacent channel power ratio(ACPR) more than 10 dB for IS-95 CDMA IFA signals.

A practial design of direct digital frequency synthesizer with multi-ROM configuration (병렬 구조의 직접 디지털 주파수 합성기의 설계)

  • 이종선;김대용;유영갑
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.12
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    • pp.3235-3245
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    • 1996
  • A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

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Design and Experiment of Ku_band Linear Active Phased Array Antenna System (Ku 대역 선형 능동 위상 배열 안테나 시스템 설계 및 실험)

  • Ryu Sung-Wook;Eom Soon-Young;Yun Jae-Hoon;Jeon Soon-Ick;Kim Nam
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.7 s.110
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    • pp.694-705
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    • 2006
  • In this paper, the linear active phased array antenna system operated in Ku DBS band was designed and experimented. The antenna system was composed of sixteen radiating active channels and Wilkinson power combiners with 16-channel inputs, a stabilizing DC bias and phase control board. Electrical beams of the antenna system can be formed by controling the phase-states of 3-bit digital phase shifter inside each active channel by virtue of the phase control board. The amplitude and phase deviations measured between active channels were less than ${\pm}0.8dB$ and ${\pm}15^{\circ}$, respectively, and the noise figure of each active channel was measured less than 1.2 dB in the operating band. The measured performances of the overall antenna system showed the antenna gain of more than 23.07 dBi and the sidelobe level of less than -11.17 dBc, and the bore-sight cross-polarization level of less than -12.75 dBc in the operating band. Also, by phase-controlling active channels, the beam scan patterns at $10^{\circ},\;20^{\circ},\;30^{\circ}$ were measured, and the losses caused by the corresponding beam scanning were 1.1 dB, 2.5 dB and 3.6 dB from the measurements, respectively.

The Active Noise Control in Harmonic Enclosed Sound Fields (I) Computer Simulation (조화가진된 밀폐계 음장에서의 능동소음제어 (I) 컴퓨터 시물레이션)

  • Oh, Jae-Eung;Lee, Tae-Yeon;Kim, Heung-Seob;Shin, Joon
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.17 no.5
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    • pp.1054-1065
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    • 1993
  • A computer simulation is performed on the effectiveness of the active minimization of harmonically excited enclosed sound fields for producing global reduction in the amplitude of the pressure fluctuations. In this study for the appreciable reductions in total time averaged acoustic potential energy, $E_{pp}$, the transducer location strategies for three dimensional active noise control is presented based on a state space modal which approximates the closed acoustic field.In this study, the above theoretical basis is used to investigate the application of active control to sound fields of low modal density. By the used of room-like 3-dimensional rectangular enclosure it is demonstrated that the reductions in $E_{pp}$ can be achieved by using a single secondary source, provided that the source is placed within the half a wavelength from the primary source and placed away from nodal line of the sound field. Concerning the reductions in $E_{pp}$ by minimzing the pressure in sound fields by the use of 3-dimensional rectangular enclosure, the effects of the number of sensors and the locations of these sensors are investigated. When a few modes dominate the response it is found that if only a limited number of sensors are located away from nodal line and located at the pressure maxima of the sound field such as at each corner of a rectangular enclosure.

Development and Performance Compensation of the Extremely Stable Transceiver System for High Resolution Wideband Active Phased Array Synthetic Aperture Radar (고해상도 능동 위상 배열 영상 레이더를 위한 고안정 송수신 시스템 개발 및 성능 보정 연구)

  • Sung, Jin-Bong;Kim, Se-Young;Lee, Jong-Hwan;Jeon, Byeong-Tae
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.6
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    • pp.573-582
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    • 2010
  • In this paper, X-band transceiver for high resolution wideband SAR systems is designed and fabricated. Also as a technique for enhancing the performance, error compensation algorithm is presented. The transceiver for SAR system is composed of transmitter, receiver, switch matrix and frequency generator. The receiver especially has 2 channel mono-pulse structure for ground moving target indication. The transceiver is able to provide the deramping signal for high resolution mode and select the receive bandwidth for receiving according to the operation mode. The transceiver had over 300 MHz bandwidth in X-band and 13.3 dBm output power which is appropriate to drive the T/R module. The receiver gain and noise figure was 39 dB and 3.96 dB respectively. The receive dynamic range was 30 dB and amplitude imbalance and phase imbalance of I/Q channel was ${\pm}$0.38 dBm and ${\pm}$3.47 degree respectively. The transceiver meets the required electrical performances through the individual tests. This paper shows the pulse error term depending on SAR performance was analyzed and range IRF was enhanced by applying the compensation technique.