• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.1
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• pp.73-79
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• 2020

Modern radar system requires high spectral purity and low phase noise characteristics for very low RCS target detection and high resolution SAR (Synthetic Aperture Radar) image. This paper presents a new X-band high stable frequency synthesizer for high performance radar system, which combines DAS (Direct Analog Synthesizer) and DDS (Direct Digital Synthesizer) techniques, in order to cope with very low phase noise and high frequency agility requirements. This synthesizer offers more than 10% operating bandwidth in X-band frequency and fast agile time lower than 1 usec. Also, the phase noise at 10kHz offset is lower than -136dBc/Hz, which shows an improvement of more than 10dB compared to the current state of art frequency synthesizer. This architecture can be applied to L-band and C-band application as well. This frequency synthesizer is able to used in modern AESA (Active Electronically Scanned Array) radar system and high resolution SAR application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.161-166
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• 1999

The global trends of mobile communication system is moving toward digitizing, high-speed and large-capacity. Also, to utilize the limited frequency-resource efficiently, spread spectrum system is a mainstream. In this study we are concerning with the fast frequency-hopping system. Instead of the PLL with many problems such as phase-noise, we used the DDS is popular in these days minimizes the disadvantage of PLL. In the case the FFH system is designed using the PLL, it is difficult to be satisfied of the design conditions such as RF badwidth and the settling time of PLL, and it has limitation because of complex circuit by using the balanced modulator. In this study, we evaluated the performance in order to design the FFH system using the DDS. The system that has the improvement of error rate, 1Mhps hopping rate and 5MHz RF bandwidth is designed and evaluated.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.267-270
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• 1999

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. In the case that ROM is used for sinusoidal value calculation, reducing the size of ROM is significant. So the power consumption is affected mostly by its bit width. In the proposed method, the ROM bit width is reduced by 1 bit using the phase subtraction and the approximation. The spurious level is better than 80㏈c and the power consumption estimated is 510㎼/MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.166-171
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• 2000

In modem wireless communication it has been regarded as a important problem for the spectrum efficiency to utilize the limited frequency-resource efficiently. In addition, the system architecture has bun designed for low cost, low power consumption and ultra-lightweight. In this paper, we directly modulated the BCPFSK with a superior spectrum efficiency using the DDS and applied the direct conversion to the system architecture. Finally, we designed a transceiver which has the 433 MHz BCPFSK output and evaluated the system performance.

• IT SoC Magazine
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• s.3
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• pp.35-37
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• 2004

본 연구팀이 Hynix 0.35um CMOS 4M 2P 공정을 사용하여 제작한 민수용 DDFS (DAC를 포함한 single chip)는 DC부터 100MHz 까지 사용할 수 있으며(BW=100MHz) frequency 변환속도 약 30nS, 주파수해상도 0.0745Hz, 그리고 소비 전력은 120MHz 클럭에서 약 200mW이다. 본고에서는 언급하지 않았지만, 본 연구팀이 별도의 설계로 진행된 군수용 DDFS의 경우, 출력주파수는 DC부터 320MHz 까지 가능하고 소비 전력은 800MHz 클럭에서 약 400mW이다. 이처럼 DDFS는 특성 자체의 우수성 뿐 아니라, 각종 멀티미디어 기기 및 통신시스템의 급격한 디지털화 추세로 인해 주파수합성기도 디지털화 함으로써 VLSI화가 용이하고, 이에 따라 S/W에 의한 다기능화 (programmability), 응용성의 극대화, 및 저가격화를 추구할 수 있다는 점에서 주목해야 할 분야이다. 특히 반도체기술의 발전으로 지금까지 DDFS 구현의 가장 큰 장애로 대두되던 DAC의 고속화가 부분적으로 가능해지면서 (TTL-to-ECL interface 부가회로가 별도로 필요없이 직접적인 연결), DDFS의 시장 전망을 더욱 밝게 하고 있다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.3
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• pp.41-51
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• 1997

In this study, two types of the direct digital frequency synthesizers (DDFS) designed and implemented using 1.0.mu.m CMOS gatearray(SOG) technolgoies are interoduced. To analize the effect of the number of phase bits(L), address data bits(A), and DAC bits (D) on the output spectrums of the DDFSs, the NCO-based BCD-DDFS composed of L=24, A=14, and D=8, and the improved binary-DDFS composed of L=24, A=8, and D=10 have been studied. The chips have been designed with and without a noise shapper to reduce spurious noises due to phase truncation and reduced sine ROM in output spectrum.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.775-784
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• 2010

In this paper we propose a design method of X band frequency hopping synthesizer in terms of phase noise and settling time with DDS driven PLL architecture, which has the advantages of high frequency resolution, fast settling time and small size. In addition, a noble method is proposed to remove the synthesizer output spurious signals due to superposition effect of DDS. The spurious signal which depend on its normalized frequency of DDS, can be dominant if they occur within the PLL loop bandwidth. We verify that the sources of that spurious signals are quasi-amplitude modulation and superposition effect, and suggest that such signals can be eliminated by intentionally creating frequency errors in the developed synthesizer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.5
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• pp.869-876
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• 2001

In modern wireless communication, it has been regarded as a important problem for the spectrum efficiency to utilize the limited frequency-resource efficiently. In addition, the system architecture has been designed for low cost, low power consumption and ultra-lightweight. In this paper, we directly modulated the BCPFSK with a superior spectrum efficiency using the DDS and applied the direct conversion to the system architecture. Finally, we designed a transceiver which has the 433 MHz BCPFSK output and evaluated the system performance. In the measured result, we know that as for spectrum and the power efficiency, BCPFSK method is better than conventional one. Also, the results of the designed system is 433.92 MHz in center frequency and about 33 dBc in carrier suppression ratio. And we get the better results in local oscillator leakage and the spurious of the ISM out-band the same as -69dBc and under 60dBc.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.50 no.2
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• pp.119-125
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• 2022

In this paper, we present design, implementation and test results of CTM (Chirp Transceiver Module) EM (Engineering Model) for C-Band SAR (Synthetic Aperture Radar) Payload. The CTM is designed to operate dual frequency scan method that simultaneously operate two frequencies in each 50MHz bandwidth to achieve 120Km swath with 10m resolution at about 500Km altitude. The CTM used radiation tolerant RTG4 FPGA for space environment, and implemented with the Parallel DDS (PDDS) method which uses a small memory capacity compared to the memory-map method. Test results show high purity chirp signal generation and excellent IRF performance from received chirp signal after direct digital conversion.