• Title/Summary/Keyword: 주파수 분배

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A Design and Fabrication of the X-Band Transmit/Receive Module for Active Phased Array SAR Antennas (능동 위상 배열 SAR 안테나를 위한 X-대역 송수신 모듈의 설계 및 제작)

  • Chong, Min-Kil;Kim, Sang-Keun;Na, Hyung-Gi;Lee, Jong-Hwan;Yi, Dong-Woo;Baik, Seung-Hun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.10
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    • pp.1050-1060
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    • 2009
  • In this paper, a X-Band T/R-module for SAR(Synthetic Aperture Radar) systems based on active phased array antennas is designed and fabricated. The T/R modules have a and width of more than 800 MHz centered at X-Band and support dual, switched polarizations. The output power of the module is 7 watts over a wide bandwidth. The noise figure is as low as 3.9 dB. Phase and amplitude are controlled by a 6-bit phase shifter and a 6-bit digital attenuator, respectively. Further the fabricated T/R module has est and calibration port with directional coupler and power divider. Highly integrated T/R module is achieved by using LTCC(Low Temperature Co-fired Ceramic) multiple layer substrate. RMS gain error is less than 0.8 dB max. in Rx mode, and RMS phase error is less than $4^{\circ}$ max. in Rx/Tx phase under all operating frequency band, or the T/R module meet the required electrical performance m test. This structure an be applied to active phase array SAR Antennas.

Simulation Methods Development for a Plant Unit Master Control Logic Using Simulink in MATLAB (매트랩 시뮬링크를 이용한 플랜트 유닛마스터 제어로직 시뮬레이션 기법 개발)

  • Yoon, Changsun;Hong, Yeon-Chan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.2
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    • pp.324-334
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    • 2017
  • The simulators for a plant unit master control (UMC) developed by domestic or overseas researchers have been developed for operator-training purposes. UMC simulators normally constructed at the end of the plant construction, despite the UMC logics, should be simulated to pre-check many signal interfaces within the power generation systems. Because of the differences in construction schedule, it is difficult for logic designers or commissioning engineers to simulate the UMC logic during the design or commissioning stage. In this background, this paper proposes a simulation method that can be used easily by plant logic designers or operators in the MATLAB Simulink programming environment. The core of the UMC is realized with a unique simulation algorithm based on mathematical analysis and functional blocks combination. In addition, an integer-based configuration was proposed to realize the plant target value control for the equipment in the logic. With these simulation methods, functions, e.g., load distribution, high-low limitations, frequency compensation, etc. were simulated. The results showed that the plant UMC logic can be simulated in Simulink without a plant simulator. The various functions proposed in this paper can provide useful information about Simulink-based simulation design for plant logic designers or commissioning engineers during the power plant construction period.

Comparison and Performance analysis of Wavelet OFDM system and FD-OFDM (웨이블릿 OFDM 시스템과 FD-OFDM 시스템 성능 비교 분석)

  • Lee, Junseo;Kim, Ji-Hoon;Kim, Whanwoo
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.34-42
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    • 2013
  • In this paper, we compare the performance of wavelet OFDM (Orthogonal Frequency Division Multiplexing) and FD-OFDM(Frequency diversity OFDM) system with conventional OFDM system. Wavelet OFDM system uses wavelet transform rather than Fourier transform and contains intermediate characteristics of CDM (Code Division Multiplexing) and OFDM. In wavelet OFDM system, inter-symbol interference (ISI) can be suppressed effectively and adjacent channel interference can be also minimized well. In FD-OFDM system, each parallel branch symbol is multiplied by the orthogonal sequence and distributed into all sub-carriers. Then, each sub-carrier transmits information composed of the symbol components of all parallel branches in the given frame. FD-OFDM contains the frequency diversity characteristic and, therefore, FD-OFDM can be robust to the narrowband interference. For the comparison among different systems, BER (Bit-Error Rate) performances are evaluated in the presence of narrow-band interference and a harmonic noise channel. From the evaluation results, compared to the conventional OFDM, wavelet OFDM and FD-OFDM shows better robustness against the interference and, especially, wavelet OFDM is the most robust in harmonic noise channel.

A New Resource Allocation with Rate Proportionality Constraints in OFDMA Systems (OFDMA 시스템에서 비율적 전송률 분배를 위한 자원 할당)

  • Han, Seung-Youp;Oh, Eun-Sung;Han, Myeong-Su;Hong, Dae-Sik
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.1
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    • pp.59-65
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    • 2008
  • In this paper, a new adaptive resource allocation scheme is proposed in orthogonal frequency-division multiple access(OFDMA) systems with rate proportionality constraints. The problem of maximizing the overall system capacity with constraints on bit error rate, total transmission power and rate-proportionality for user requiring different classes of service is formulated. Since the optimal solution to the constrained fairness problem is extremely complex to obtain, a low-complexity suboptimal algorithm that separates subchannel allocation and power allocation is proposed. Firstly, the number of subchannels to be assigned to each user is determined based on the users' average signal-to-noise ratio and rate-proportion. Subchannels are subsequently distributed according to the modified max-min criterion. Lastly, based on the subchannel allocation, the optimal power allocation by solving the Language dual problem is proposed. Additionally, in order to reduce the computational complexity, iterative rate proportionality tracking algorithm is proposed for maximizing the capacity together with maintaining the rate proportionality constraint.

A design method for optical fiber filter of lattice structure (격자형 광파이버필터의 설계에 관한 연구)

  • 이채욱;문병현;김신환
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.9
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    • pp.1248-1256
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    • 1993
  • The propagation and delay properties in opical fiber are particularly attractive because digital signal processing and conventional analog signal processing techniques such as those using surface acoustic wave devices are limited In their usefulness for signal bandwidth exceeding one or two GHz, although they are very effective at lower frequencies. Since an accurate, low loss and short time delay elements can be obtained by using such an optical fiber, optical signal precessing has attracted much attention for high speed and broad-band signal precessing in particular channel separation filtering for optical FDM signals. In this paper, we consider a coherent optical lattice filter, which uses coherent light sources and consists of directional couplers and optical fiber delay elemnts. The optical fiber fitters are more restricted than the usual digital filters. The reasons are as follows. 1) the coupling coefficients of directional couplers are restricted to the number between 0 and 1. 2) optical signal E(complex amplitude) is divided into J If-$\boxUl$ and J L/7$\div$$\boxUl$ at the directional coupler. Considering these restrictions and in this case all the coupling coefficients of summing and branching elements are set to be equal, we have given design formulae for optical lattice filter, which make the best use of optical signal energy.

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A Low Jitter Delay-Locked Loop for Local Clock Skew Compensation (로컬 클록 스큐 보상을 위한 낮은 지터 성능의 지연 고정 루프)

  • Jung, Chae-Young;Lee, Won-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.2
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    • pp.309-316
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    • 2019
  • In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.