• Title/Summary/Keyword: 주파수할당

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Hardware Design of Rate Control for H.264/AVC Real-Time Video Encoding (실시간 영상 부호화를 위한 H.264/AVC의 비트율 제어 하드웨어 설계)

  • Kim, Changho;Ryoo, Kwangki
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.12
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    • pp.201-208
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    • 2012
  • In this paper, the hardware design of rate control for real-time video encoded is proposed. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. For high speed and low computational prediction, the MAD is predicted based on the coded basic unit, using spacial and temporal correlation in sequences. The rate control is designed with the hardware for fast QP decision. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. In addition, the rate control is designed with the hardware for fast QP decision. The execution cycle and gate count of the proposed architecture were reduced about 65% and 85% respectively compared with those of previous architecture. The proposed RC was implemented using Verilog HDL and synthesized with UMC $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count of the architecture is about 19.1k with 108MHz clock frequency.

A RFID Tag Anti-Collision Algorithm Using 4-Bit Pattern Slot Allocation Method (4비트 패턴에 따른 슬롯 할당 기법을 이용한 RFID 태그 충돌 방지 알고리즘)

  • Kim, Young Back;Kim, Sung Soo;Chung, Kyung Ho;Ahn, Kwang Seon
    • Journal of Internet Computing and Services
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    • v.14 no.4
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    • pp.25-33
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    • 2013
  • The procedure of the arbitration which is the tag collision is essential because the multiple tags response simultaneously in the same frequency to the request of the Reader. This procedure is known as Anti-collision and it is a key technology in the RFID system. In this paper, we propose the 4-Bit Pattern Slot Allocation(4-BPSA) algorithm for the high-speed identification of the multiple tags. The proposed algorithm is based on the tree algorithm using the time slot and identify the tag quickly and efficiently through accurate prediction using the a slot as a 4-bit pattern according to the slot allocation scheme. Through mathematical performance analysis, We proved that the 4-BPSA is an O(n) algorithm by analyzing the worst-case time complexity and the performance of the 4-BPSA is improved compared to existing algorithms. In addition, we verified that the 4-BPSA is performed the average 0.7 times the query per the Tag through MATLAB simulation experiments with performance evaluation of the algorithm and the 4-BPSA ensure stable performance regardless of the number of the tags.

The Design of Optimal Filters in Vector-Quantized Subband Codecs (벡터양자화된 부대역 코덱에서 최적필터의 구현)

  • 지인호
    • The Journal of the Acoustical Society of Korea
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    • v.19 no.1
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    • pp.97-102
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    • 2000
  • Subband coding is to divide the signal frequency band into a set of uncorrelated frequency bands by filtering and then to encode each of these subbands using a bit allocation rationale matched to the signal energy in that subband. The actual coding of the subband signal can be done using waveform encoding techniques such as PCM, DPCM and vector quantizer(VQ) in order to obtain higher data compression. Most researchers have focused on the error in the quantizer, but not on the overall reconstruction error and its dependence on the filter bank. This paper provides a thorough analysis of subband codecs and further development of optimum filter bank design using vector quantizer. We compute the mean squared reconstruction error(MSE) which depends on N the number of entries in each code book, k the length of each code word, and on the filter bank coefficients. We form this MSE measure in terms of the equivalent quantization model and find the optimum FIR filter coefficients for each channel in the M-band structure for a given bit rate, given filter length, and given input signal correlation model. Specific design examples are worked out for 4-tap filter in 2-band paraunitary filter bank structure. These optimum paraunitary filter coefficients are obtained by using Monte Carlo simulation. We expect that the results of this work could be contributed to study on the optimum design of subband codecs using vector quantizer.

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A New Incentive Based Bandwidth Allocation Scheme For Cooperative Non-Orthogonal Multiple Access (협력 비직교 다중 접속 네트워크에서 새로운 인센티브 기반 주파수 할당 기법)

  • Kim, Jong Won;Kim, Sung Wook
    • KIPS Transactions on Computer and Communication Systems
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    • v.10 no.6
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    • pp.173-180
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    • 2021
  • Non Orthogonal Multiple Access (NOMA) is a technology to guarantee the explosively increased Quality of Service(QoS) of users in 5G networks. NOMA can remove the frequent orthogonality in Orthogonal Multiple Access (OMA) while allocating the power differentially to classify user signals. NOMA can guarantee higher communication speed than OMA. However, the NOMA has one disadvantage; it consumes a more energy power when the distance increases. To solve this problem, relay nodes are employed to implement the cooperative NOMA control idea. In a cooperative NOMA network, relay node participations for cooperative communications are essential. In this paper, a new bandwidth allocation scheme is proposed for cooperative NOMA platform. By employing the idea of Vickrey-Clarke-Groves (VCG) mechanism, the proposed scheme can effectively prevent selfishly actions of relay nodes in the cooperative NOMA network. Especially, base stations can pay incentives to relay nodes as much as the contributes of relay nodes. Therefore, the proposed scheme can control the selfish behavior of relay nodes to improve the overall system performance.

Impact of Channel Estimation Errors on SIC Performance of NOMA in 5G Systems (5G 시스템에서 비직교 다중접속의 SIC 성능에 대한 채널 추정 오류의 영향)

  • Chung, Kyuhyuk
    • Journal of Convergence for Information Technology
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    • v.10 no.9
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    • pp.22-27
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    • 2020
  • In the fifth generation (5G) networks, the mobile services require much faster connections than in the fourth generation (4G) mobile networks. Recently, as one of the promising 5G technologies, non-orthogonal multiple access (NOMA) has been drawing attention. In NOMA, the users share the frequency and time, so that the more users can be served simultaneously. NOMA has several superiorites over orthogonal multiple access (OMA) of long term evolution (LTE), such as higher system capacity and low transmission latency. In this paper, we investigate impact of channel estimation errors on successive interference cancellation (SIC) performance of NOMA. First, the closed-form expression of the bit-error rate (BER) with channel estimation errors is derived, And then the BER with channel estimation errors is compared to that with the perfect channel estimation. In addition, the signal-to-noise (SNR) loss due to channel estimation errors is analyzed.

A Unified Time-domain Channel Estimator for OFDM based Ubiquitous Broadband Access (OFDM 기반의 유비쿼터스 광대역 접속을 위한 단일화 시간영역 채널 추정기)

  • Seo, Jeong-Wook;Kwak, Jae-Min;Kim, Dong-Ku
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.1
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    • pp.19-24
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    • 2010
  • This paper proposes a unified time-domain channel estimator (UTD-CE) for ubiquitous wireless broadband access based on orthogonal frequency division multiplexing (OFDM) systems. As a part of a software radio platform for ubiquitous services, the proposed UTD-CE can be exploited with the simply changeable parameters, pilot symbols and pilot subcarriers allocation, which are usually different according to the system specifications such as IEEE802.11x WiFI, IEEE802.16x WiMAX, DMB, Media FLO, DVB-H, etc. Given the pilot information, the channel frequency responses (CFRs) of data subcarriers will be analogously estimated by Wiener filtering and discrete Fourier transform (DFT)-based interpolation in the UTD-CE. Simulation results indicate that the proposed method significantly outperforms the conventional time-domain channel estimator when the pilot information is changed.

A Power Control for OFDM Transmission Scheme in a Cochannel Interference Environment (동일 채널 간섭 환경에서 OFDM 전송 방식을 위한 송신 전력 제어)

  • Park, Jin-Kyu;Lim, Chang-Heon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.3A
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    • pp.271-280
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    • 2007
  • This paper presents a power control scheme for OFDM based wireless communication systems in a multicell environment with co-channel interference which enables each system to achieve its target level of transmission bit rate. Generally, the optimal or near optimal power control scheme for multicarrier systems is Down to control the power level of each subcarrier in accordance with the associated channel status, which may be found in WF(waterfilling) and WF(iterative waterfilling) schemes. However, this requires the channel state information associated with every subchannel to be fed back from the receiver to its transmitter for successful power control. If the wireless channel exhibits relatively fast fading or the number of subcarriers is large, this may result in a considerable overhead. Here, in order to alleviate this problem, we propose a power control strategy for an OFDM systems maintaining the same power level over all the subcarriers. Also we prove its convergence, compare its complexity with that of the existing IWF algorithm, and examine its convergence characteristic through computer simulations.

Digit-serial VLSI Architecture for Lifting-based Discrete Wavelet Transform (리프팅 기반 이산 웨이블렛 변환의 디지트 시리얼 VLSI 구조)

  • Ryu, Donghoon;Park, Taegeun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.1
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    • pp.157-165
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    • 2013
  • In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

Dual Mode Packet Transmission Scheme using a Dynamic Switching Threshold in the IMT-2000 (IMT-2000에서 동적 스위칭 임계점을 이용하는 이중 모드 패킷 전송방식)

  • 김장욱;반태원;오창헌;조성준
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.5
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    • pp.907-915
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    • 2003
  • A very efficient packet transmission scheme is needed in the radio environment where radio resource is insufficient as compared with the environment of the wired communication. In general, dual mode packet transmission scheme is used broadly. Packets are transmitted through the dedicated or common chamois according to a switching criterion. The general criteria are the length and generation frequency of packet, that is, large and frequent packets are transmitted using a dedicated channel and small and infrequent packets are transmitted using a common channel. The performance of dual mode packet transmission scheme is closely related to the switching criteria. However, it is very difficult to find the optimal switching point because that is not fixed but variable according to the environment such as traffic load, length of generated packets, and the number of channels. In this paper, a new scheme for the dual mode packet transmission scheme using a dynamic switching threshold is proposed where the switching threshold is not fixed but variable according to the network environment. The performance of the proposed method is analyzed using a simulation. From the simulation results, it is shown that the performance of the proposed scheme is not very influenced by the network environment unlike the conventional dual mode packet transmission scheme.

Performance Evaluation of Initial Cell Search Scheme Using Time Tracker for W-CDMA (시간 동기 블록을 적용한 비동기 W-CDMA용 초기 셀 탐색 방법의 성능 분석)

  • Hwang, Sang-Yun;Kang, Bub-Ju;Choi, Woo-Young;Kim, Jae-Seok
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.1B
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    • pp.24-33
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    • 2002
  • The cell search scheme for W-CDMA consists of the following three stages: slot synchronization(1st stage), group identification and frame boundary detection(2nd stage), and long code identification(3rd stage). The performance of the cell search when a mobile station is switched on, which is referred to as initial cell search, is decreased by the initial frequency and timing error. In this paper, we propose the pipeline structured initial cell search scheme using time trackers to compensate for the impact of the initial timing error in the stage 2 and stage 3. The simulation results show that the performance of the proposed scheme is maximal 1.5dB better than that of the conventional one when the initial timing error is near ${\pm}T_c$/2.