• Proceedings of the Korea Society for Industrial Systems Conference
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• 1999.05a
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• pp.75-79
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• 1999

다치결정도(Multiple-valued Decision Diagram : MDD)와 순서화된 다치결정도(Ordered MDD : OMDD)는 다치논리함수의 표현에 폭넓게 사용된다. p치 n변수 인 경우 p$^{(n-1)}$ 으로 증가하는 노드의 수는 ROMDD(Reduced OMDD)를 사용하여 현저하게 감소시킬 수 있다. 그러나 다치와 다변수의 경우에는 더욱 많은 공정을 수반하게 된다. 이러한 단점을 보완하기 위해 Honghai Jiang이 제안한 2치시스템에서의 input implict/output explicit 관계를 갖는 OVAG(Output Value Array Graph)를 사용하여 다치논리함수를 표현한다. 고리고 MDD 표현이 어려운 상황에서 MOVAG(Multi OVAG)를 사용하여 보다 쉽게 출력값을 배열하는 그래프를 이끌어 낼 수 있다. 본 논문에서는 MOVAG의 구성방법과 회로에서 MOVAG로의 변환에 대한 알고리즘을 제안하였고, 알고리즘에 의한 결과를 MDD와 비교하여 노드수 감소에 따르는 처리속도가 개선됨 을 검증하였다.

• Journal of Korean Philosophical Society
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• v.139
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• pp.1-21
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• 2016

To quickly and accurately grasp the consistency and the true/false of sentence description, we may require the help of a computer. It is thus necessary to research and quickly and accurately grasp the consistency and the true/false of sentence description by computer processing techniques. This requires research and planning for the whole study, namely a plan for the necessary tables and those of processing, and development of the table of the five logic rules. In future research, it will be necessary to create and develop the table of ten basic inference rules and the eleven kinds of derived inference rules, and it will be necessary to build a DB of those tables and the computer processing of sentence logic using server programming JSP and client programming JAVA over its foundation. In this paper we present the overall research plan in referring to the logic operation table, dividing the logic and inference rules, and preparing the listed process sequentially by dividing the combination of their use. These jobs are shown as a variable table and a symbol table, and in subsequent studies, will input a processing table and will perform the utilization of server programming JSP, client programming JAVA in the construction of subject/predicate part activated DB, and will prove the true/false of a sentence. In considering the table prepared in chapter 2 as a guide, chapter 3 shows the creation and development of the table of the five logic rules, i.e, The Rule of Double Negation, De Morgan's Rule, The Commutative Rule, The Associative Rule, and The Distributive Rule. These five logic rules are used in Propositional Calculus, Sentential Logic Calculus, and Statement Logic Calculus for sentence logic.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.29-38
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• 1999

This paper presents a new algorithm RICP(Redundancy Identification using Critical-pair Paths) to identify untestable faults in combinational logic circuits. In a combinational logic circuit, untestable faults occurred by redundancy of circuits. The redundancy of a circuit can be detected by analyzing areas of fanout stem and reconvergent gates. The untestable faults are identified by analyzing stem area using Critical-Pair path which is an extended concept of critical path. It is showed that RICP is better than FIRE(Fault Independent REdundancy identification) algorithm in efficiency. The performance of both algorithms was compared using ISCAS85 bench mark testing circuits.

• The Journal of Korean Association of Computer Education
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• v.10 no.4
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• pp.17-25
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• 2007

In this paper, the simplification procedure of Karnaugh Map, which is essential to design digital logic circuits, was implemented as a web-based educational tool by Java applet. The learners can make virtual experiments on the simplification of the digital logic circuit by clicking on some buttons or filling out some text fields. The proposed simplification procedure was implemented as a Java applet which is based on the Modified Quine-McCluskey algorithm. Thus, the implemented Java applet will enable the learners to enhance the learning efficiency as a auxiliary educational tool.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.209-212
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• 2000

This paper describes the design and implementation of a hard- wired AGV controller using CPLD(Complex Programmable Logic Device). The proposed controller manages a guidance equipment, motor and I/O sequence controller for a self-control traveling. Compared with a conventional $\mu$-processor, the CPLD controller using a hard-wired control method can reduce a difficult programming process. Also, the total costs of production are reduced, such as development time, product's size and difficulty because memory, combinational logic and sequential logics are implemented by CPLD. The Controller designed using behavioral description method with VHDL and was synthesized by MAX＋Plus II of the ALTERA co. We implemented controller using EPF10K10LC84-4 device.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.1027-1030
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• 2015

하드웨어 디자인 설계에서 초기 단계의 설계 오류 발견은 개발 비용 감소 및 설계 시간 단축 측면에서 그 효과가 매우 크다. 이러한 초기 설계 오류 발견을 위한 대표적인 방법으로는 정형 검증(formal verification)이 있으며, Cadence SMV(Symbolic Model Verifier)는 정형 검증을 위해 Verilog HDL(Hardware Description Language)을 SMV로 자동 변환 해주는 장점이 있지만, 사건 기반 구조(event based structures)의 sensitivity list에 대한 지원을 하지 않는 한계가 있다. 이에 본 논문에서는 Cadence SMV에서 디지털회로(digital circuit) 중 하나인 조합 논리회로(combinational logic circuit)를 sensitivity list가 고려된 검증이 가능하도록 하는 방법을 제안한다. 신뢰성 있는 실험을 위해 본 논문에서는 제안하는 방법의 일반적인 규칙을 도출하였고, 도출된 규칙이 적용된 SMV 파일을 생성하는 자동화 프로그램을 구현하여 실험하였다. 실험결과 제안한 방법을 적용한 경우 기존 Cadence SMV가 발견하지 못한 설계상의 오류를 발견할 수 있었다.

• Journal for History of Mathematics
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• v.20 no.4
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• pp.61-70
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• 2007

Combinatorics, often called the 21 st century mathematics, has turned out a very important subject for the present information era. Modern combinatorics has started from some mathematical works, for example, Pascal's triangle and the binomial coefficients, and Euler's problems on the partitions of integers and Konigsberg's bridge problem, and so on. In this paper, we investigate the origin of combinatorics by looking over some interesting ancient combinatorial problems and some important problems which have started various subfields of combinatorics. We also discuss a little on the role of combinatorics in mathematics and mathematics education.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of The Korean Association For Science Education
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• v.9 no.1
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• pp.101-111
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• 1989

본 연구의 목적은 광합성과 관련하여 한국 국민학교 5학년과 중학교 2학년 학생들이 갖고 있는 오개념을 조사하고, 학생들의 개념이해 정도, 논리적 사고능력, 그리고 학생배경변수들 사이의 상호관계를 조사하는 것이다. 세가지의 도구들이 이 연구를 위해 개발되었다. 광합성 개념검사 (Photosynthesis Concepts Test)는 광합성과 관련된 개념들의 이해를 평가하기 위해, 삐아제의 논리적 사고력 검사(Piagetian Cogical Reasoning Test)는 PCT에 포함된 3종류의 논리적 사고들, 변인 통제, 조합적 사고력, 상관관계 사고능력을 평가하기 위해, 그리고 실문서는 학생들의 배경변수들에 대한 정보를 얻기 위해 개발되었다. 이 도구들은 20명 의 국민학교 5학년, 239명의 중학교 2학년 학생들에게 시행되었다. 이 연구의 결과는 두집단의 학생들이 "먹이를 만든다"는 의미, 먹이의 정의, 식물에 의한 빛의 사용, 식물 뿌리와 잎의 기능들, 광합성 산물, 그리고 광합성을 위한 조건들과 관련하여 오개념을 갖고 있음을 보여 주었다. 국민학교 5학년과 중학교 2학년 사이의 개념 이해의 향상은 식물에 의한 빛 이용의 본질, 한 체계내에서 생물들간의 물질 교환, 포도당, 지방, 단백질 등에 대한 지식에서 보여졌고, 그래프를 해석하는 능력에서 또한 중학교 2학년 학생들이 앞섰다. 향상을 보인 항목들은 교과서에서 보다 많은 강조점을 두거나 상위의 논리적 사고능력을 요구하는 것들이었다. 희귀분석 결과, 전년도 과학성적과 논리적 사고력이 PCT 성취도에 가장 예견력이 높은 두 변수이며 5학년의 경우 성취도의 약 22%의 변량을, 중2의 경우 성취도의 약 40%의 변량을 설명하였다. 후속연구로서 내용의 추상성, 적절성, 그리고 요구되는 논리적 능력면에서 교수조건의 변형을 통한 오개념의 변화와 감소에 대한 실험적 연구가 제시되었다.