• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.734-737
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• 2008

This paper presents a new automatic TFT-LCD image quality optimization system. We also have developed new algorithms using 6-point programmable matching technique with reference gamma curve, and automatic power setting sequence. It optimizes automatically gamma adjustment and power setting registers in mobile TFT-LCD driver IC to reduce gamma correction error, adjusting time, and flicker. Developed algorithms and programs are generally applicable for most of the TFT-LCD modules. The proposed optimization system contains module-under-test (MUT, TFT-LCD module), control program, multimedia display tester for measuring luminance and flicker, and control board for interface between PC and TFT-LCD module. The control board is designed with DSP, and it supports various interfaces such as RGB and CPU. Developed automatic image quality optimization system showed significantly reduced gamma adjusting time, reduced flicker, and much less average gamma error than competing system. We believe that the proposed system is very useful to provide high image quality TFT-LCD and to reduce developing process time using optimized gamma-curve setting and automatic power setting.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.474-476
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• 1998

전송 프로토콜은 응용 프로그램과 네트워크의 인터페이스로서, 응용 프로그램에서 요구한 QoS(Quality of Service)를 제공하는 역할을 한다. 이 중 TCP는 인터넷의 전송 흐름 제어를 위해서 사용되는 프로토콜이다. TCP의 흐름 제어를 위해서 수신된 데이터의 ACK(acknowledgement)에 따라 허가된 윈도크기만큼의 데이터를 보내는 크레디트 할당 밀집 윈도(congestion window)를 사용한 slow-start 알고리즘을 사용하며, 손실된 데이터를 재전송하기 위한 방법으로 빠른 재전송 및 회복 알고리즘을 사용한다. 본 논문에서는 빠른 재전송 알고리즘에서 나타나는 문제점을 알아보고, 이 알고리즘이 빠른 시간에 데이터 손실을 회복하고 데이터를 보낼 수 있도록 수정한 알고리즘을 소개한다. 또한 수정된 알고리즘을 확장하여 네트워크의 상태에 따라 더 많은 데이터를 보낼 수 있도록 개선한 알고리즘을 제안한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.48-61
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• 2017

An IaaS service of a cloud computing environment makes itself attractive for running large scale parallel application thanks to its innate characteristics that a user can utilize a desired number of high performance virtual machines without maintenance cost. The total execution time of a parallel application on a high performance computing environment depends on a task scheduling algorithm. Most studies on task scheduling algorithms on cloud computing environment try to reduce a user cost, and studies on task scheduling algorithms that try to reduce total execution time are rarely carried out. In this paper, we propose a task scheduling algorithm called an HAGD and a performance enhancement method called a group task duplication method of which the HAGD utilizes. The group task duplication method simplifies previous task duplication method, and the HAGD uses the group task duplication method or a task insertion method according to the characteristics of a computing environment and an application. We found that the proposed algorithm provides superior performance regardless of the characteristics in terms of normalized total execution time through performance evaluations.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.11a
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• pp.701-704
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• 2004

일반적으로 프로그램의 수행과정은 직관적으로 파악하기 어려워, 이에 대한 이해를 돕기 위하여 시각화 분야에 대한 다양한 연구가 필요하다. 시각화는 프로그램의 디버깅이나 개선에도 효과적으로 이용될 수 있을 뿐 아니라 컴퓨터 교육 분야에서도 폭넓게 활용될 수 있다. 본 논문에서 제안하는 시스템은 C 언어로 작성된 프로그램에 간단한 시각화 명령을 추가하고 이를 자동 변환하여 SVG 애니메이션 코드를 생성한다. 생성된 애니메이션 코드는 웹 브라우저 상에서 실행될 수 있으며 알고리즘 시각화를 위한 별도의 프로그램 작성 없이 기존 알고리즘에 간단한 명령어를 추가하여 시각화할 수 있다는 장점이 있다.

• Spatial Information Research
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• v.17 no.1
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• pp.25-37
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• 2009

In this paper, we propose techniques for hazard analysis of curved road based on USN. The techniques consist of models and algorithms. Models of curved road, road direction, sensor, vehicle and hazard are proposed. To analyze hazard in curved road and give warning to corresponding vehicle in realtime multi-level algorithms are proposed. An application program implements the models and algorithms to simulate proposed techniques with real-time visualization.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.875-877
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• 2015

IoT 환경의 센서 네트워크와 RFID 태그 등에서의 AES나 SEED에 대응 할 수 있는 새로운 저전력 경량화 암호 알고리즘이 필요 해짐에 따라 본 논문에서는 2006년 국내에서 제안된 HIGHT와 2007년 CHES에서 제안된 PRESENT 알고리즘을 Arduino에 적용하여 성능을 비교분석 하였다. 그 결과 HIGHT 알고리즘이 PRESENT알고리즘에 비하여 더 짧고, 적은 수행시간과 프로그램 메모리 사용량을 보였으며, 더 많은 동적 메모리 사용량을 보였다.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.59-66
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• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.4
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• pp.93-99
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• 2008

Portable devices generally have limited energy sources, so there is a need to minimize the power consumption of processor using energy conservation methods. One of the most common energy conservation methods is dynamic voltage scaling (DVS). In this paper, we propose a new DVS algorithm which uses workload of application to determine frequency and voltage of processors. The posed DVS algorithm consists of DVS module in kernel and specified function in application. The DVS module monitors the processor utilization and changes frequency and voltage periodically. The other part monitors workload of application. With these two procedures, the processor can change the performance level to meet their deadline while consuming less energy. We implemented the proposed DVS algorithm on PXA270 processor with Linux 2.6 kernel.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.871-875
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• 2009

A software birthmark is inherent characteristics that can be used to identify a program. In this paper, we propose a new Java birthmark based on control flow graph (CFG) matching. The CFG matching consists of node matching and edge matching. To get similarities of nodes and edges of two CFGs, we apply a sequence alignment algorithm and a shortest path algorithm, respectively. To evaluate the proposed birthmark, we perform experiments on Java programs that implement various algorithms. In the experiments, the proposed birthmark shows not only high credibility and resilience but also fast runtime performance.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.484-486
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• 2002

이 논문에서는 자바 카드를 위한 통합 테스트 및 디버깅 환경에 대해 기술하고 있으며, 제안한 통합 개발 환경은 J-JCRE (Java language based Java Card Runtime Environment) 와 Java Card API (Application Programming Interface)로 구성되어 있다. 또한, 개발 환경은 현재 두 가지 암호 알고리즘을 지원해주며, 스크립트 실행, 시스템 클래스의 소스 레벨 디버깅, 클라이언트/서버 skeleton 자동 생성 등 다양한 기능을 제공해 준다. 제안한 통합 개발 환경을 이용함으로써 사용자들은 실제 자바 카드에 응용 프로그램을 탑재하기 전에 응용 프로그램 테스트 및 디버깅을 통해 프로그램상의 오류 밀 에러를 미리 점검하여 수정할 수 있게 된다.