• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.75-81
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• 2004

AE-CORDIC improves the CORDIC operation speed with a rotation direction pre-computation algorithm. Its CORDIC iteration stages consist of non-predictable rotation direction states and predictable rotation stages. The non-predictable stages are replaced with lookup-table which has smaller hardware size than CORDIC iteration stages. The predictable stages can determine rotation direction with the input angle and simple encoder. In this paper, a rotation direction pre-computation algorithm with input angle encoder is proposed. and AE-CORDIC which have optimized Lookup-table is compared with the P-CORDIC algorithm. Hardware size, delay, and SQNR of the AE-CORDIC are verified with Samsung 0.18㎛ technology and Synopsys design compiler when input angle bit length is 16.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.526-531
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• 2003

Recently, many BIST(Built-in Self Test) schemes have been researched to reduce test time and hardware. But, most BIST schemes about pattern generation are for deterministic pattern generation. In this paper a new pseudo-random BIST scheme is provided to reduce the existing test hardware and keep a reasonable length of test time. Theoretical study demonstrates the possibility of the reduction of the hardware for pseudo-random test with some explanations and examples. Also the experimental results show that in the proposed test scheme the hardware for the pseudo-random test is much less than in the previous scheme and provide comparison of test time between the proposed scheme and the current one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.62-71
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• 2002

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. the instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. The proposed DPU (Data Processing Unit) supporting the instructions shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 ${\mu}m$ standard cell library. The maximum operating clock frequency is about 144.5 MHz.

• Journal of IKEEE
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• v.23 no.3
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• pp.984-987
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• 2019

Recently, autonomous driving technology based on object recognition and lane recognition has attracted attention. However, in foggy weather, haze removal technology is needed because it is difficult to recognize surrounding objects. The technology of removing hazy is currently being studied in many ways, and a single image based haze removal algorithms are typical. In this paper, we design the hardware for haze removal by estimating the hazy partical map. Proposed hardware architecture is designed to have a cumulative histogram based filter that does not affect the hardware size even if the window size of filter increases. The hardware design is implemented with XILINX's xc7z045-ffg900 as the target board.

• Journal of IKEEE
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• v.27 no.3
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• pp.296-302
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• 2023

As Multimedia industry has evolved, it has become possible to display resolutions in various formats. Therefore, the performance of a scaler algorithm that converts resolutions while maintaining high quality and its hardware implementation are important. Considering the hardware design of an image up/down scaler, this paper proposes a combinatorial scaler algorithm that uses modified bilinear interpolation in the vertical direction and bicubic interpolation in the horizontal direction to reduce the line memory burden. Through quantitative and qualitative evaluations, this paper compared the performance of the proposed algorithm with three other well-known algorithms, and also compared the hardware burden of its hardware implementation. This paper used a sinusoidal signal and eight typical images for performance evaluation.

• Journal of IKEEE
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• v.28 no.1
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• pp.26-32
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• 2024

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.277-279
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• 2002

전자상거래, 무선 인터넷 등의 활성화를 위해서는 신뢰성 있는 통신 서비스를 제공하는 IPv6용 보안시스템이 필요하다. 이를 위한 기존의 암호화 알고리즘은 소프트웨어 및 하드웨어로 많이 구현되어 있으나 IPv4를 기반으로 한 운영체제에 종속되어 있다. 이를 해결하기 위하여 운영체제 없이 고성능의 보안서비스를 제공하는 IPv6용 보안시스템이 하드웨어로 구현되었다. 본 논문에서는 이러한 IPv6용 하드웨어 보안시스템에 요구되는 암호화알고리즘 중에서 HMAC-SHA-1을 하드웨어 모듈로 구현하였다. 그리고 구현한HMAC-SHA-1 모듈에 대하여 시뮬레이션 테스트를 수행하고 IPv6 하드웨어 보안시스템과 연동함으로써 기능을 검증하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.1
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• pp.53-63
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• 2000

전자지불 프로토콜은 하드웨어 구현의 용이성과 안전성의 두 가지 측면을 고려하여 설계되어야 한다. 본 논문에서 제안하는 전자지불 프로토콜은 하드웨어구현을 용이하게 하고 유지비용을 줄이기 위해 초기변수값을 최소로 하는 전자지불 프로토콜에 대칭키 암호알고리즘을 적용하여 주고받는 데이터량을 줄였으며, 안전성을 증가시키기 위해 타원곡선 공개키 암호 알고리즘을 적용하여 타원곡선 공개키 암호 알고리즘이 가지는 특성들을 상속받고록 하였고, 마지막으로 전자지불 프로토콜의 안전성과 효율성을 분석하였다.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.669-678
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• 2002

Currently, the domestic interests on the development of eyesight related measuring instruments are being increased. So we are developing such an electronic system of Refracto-keratometer, which contains a software and a hardware both. If this system could inform the examiner of the precise eyesight measuring result from the treatment of the image of optical system, then potentially the number of missed measuring results could be reduced. Our electronic system has been developed from the two areas divided into a software and a hardware. The software area was focused on the more exact eyesight measuring results, using morphological filtering methods and gray-leveled signal enhancing techniques. The hardware area is performing the same functions as the existing other systems. Besides, it provides the embedded software with free variables which could reduce the developing duration sharply as well as enlarge many kinds of application-extensions. Therefore, this electronic system has made effective eyesight measurement possible as the result of reducing the differences applied to sophisticated eyesight measurement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.11
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• pp.1094-1103
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• 2014

In this paper, we survey the works related to the system architecture of avionics and extract characteristics from the related works. On the basis of the investigation, we propose an integrated modular avionics (IMA) architecture that can be used for current avionic upgrades and future avionic developments based on the IMA Core system. To verify the feasibility of the proposed IMA architecture, we have developed the prototype of the IMA Core system that consists of both the common hardware module and the IMA software. It was verified that the developed prototype with the common hardware module contributes to the improvement of maintainability because it can save the time and expenses for the development and can reduce the number of types of hardware modules when compared with Federated architecture. It was also confirmed that the developed prototype can save not only overall system weight, size, and power consumption but also the number of hardware types because the IMA software can support the integrated processing where the single processing hardware module can process multiple software applications.