• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.3
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• pp.509-520
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• 2023

In this paper, the structure and the characteristics of the Fly-By-Wire system applied to the civil aircraft was described. The development trend of the redundant method of the flight control system, data communication system, control surface actuation system and the control laws implemented by the Fly-By-Wire system of the civil aircraft are discussed. The Fly-By-Wire system was first applied to the fighter and its inherent advantages lead to the advent of the Fly-By-Wire civil aircraft. Recently even the small jet aircraft shows the trend of adopting the Fly-By-Wire system. In the future, most of the aircraft are expected to be the Fly-By-Wire type.

• Current Industrial and Technological Trends in Aerospace
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• v.7 no.2
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• pp.85-94
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• 2009

The Fly-By-Wire system was first applied to the fighter and its inherent advantages lead to the advent of the Fly-By-Wire civil aircraft. Recently even the small jet aircraft shows the trend of adopting the Fly-By-Wire system. In the future, most of the aircraft are expected to be the Fly-By-Wire type. In this paper, the structure and the characteristics of the Fly-By-Wire system applied to the civil aircraft was described. The development trend of the redundant method of the flight control system, data communication system, control surface actuation system and the control laws implemented by the Fly-By-Wire system of the civil aircraft are discussed.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.