• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.2
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• pp.178-186
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• 2004

This paper proposes a two-phase RCD-PWM scheme which is much better than a three-phase RCD-PWM scheme from the standpoint of the broadening and linearizing effect of the power spectrum. To implement the proposed scheme and conventional scheme, the experiment based on the SAB-Cl67 micro-controller was executed. Based on the space vector modulation technique, the duty ratio of the pulses is calculated using the SAB-Cl67 and each of PWM pulses is located randomly in each switching interval. The power spectrum of the output voltage, output current, the d.c link current and the acoustic noise radiated from inverter drives are experimentally investigated. 1'hen, the performance of the proposed scheme was compared and discussed with the conventional scheme.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.4
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• pp.273-279
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• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1016-1017
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• 2006

프로세스 제어기에서 전원장치의 건전성과 신뢰성은 아무리 강조해도 지나치지 않을 것이다. 본 논문은 전원장치의 고장 감시장치에 관한 것으로, 직류 전원공급 시스템의 신뢰도 향상을 위하여 사용하는 이중화 전원 구성용 블로킹다이오드의 고장 감시 장치에 관한 것이다. 이중화 전원 공급장치에 있어서 2개의 공급전원 중 어느 한쪽의 공급전원이 상실되더라도 나머지 한쪽의 공급전원이 건전하면 정상적으로 부하에 전원을 공급하게 하기 위하여 블로킹다이오드를 사용한다. 그러나 블로킹다이오드에 고장이 발생한 경우, 전원공급장치 자체는 정상이더라도 이중화 기능을 하지 못하므로, 블로킹다이오드의 정상 여부를 상시 감시하여 이상이 발생시 경보처리 한다면 예기치 않은 전원공급 중단을 피할 수 있을 것이다. 블로킹다이오드에 흐르는 전류와 다이오드의 양단 전압을 상시 감시/계측하여 정상운전특성곡선과 비교하여, 이상이 있을 경우 이를 경보하여 전원중단을 예방할 수 있는 이중화 전원용 블로킹다이오드의 고장 감시 장치에 관한 것이다.

• Proceedings of the KIEE Conference
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• 2007.04b
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• pp.117-120
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• 2007

본 논문은 메탈헬라이드 램프들의 이그니션 특성 비교 분석을 위하여 이그니션 구간에서의 전압, 전류 및 순시임피던스(time varying resist ante), 순시전력(time varying power)을 측정하고 분석하였고, 측정 및 분석을 위하여 램프의 종류(B형, BT형)와 제조회사가 다른 램프 6종을 선택하여 사용하였다. 분석결과, 제조회사별, 램프 상태 둥에 따라 이그니션 특성이 매우 상이하게 나타났으며, 대부분의 램프 이그니션 전류가 40[A]를 상회하고 있고, 특히 몇몇 램프의 이그니션 전류는 50[A] 이상으로 나타났다 따라서 메탈헬라이드 램프들의 이그니션 전류는 정상상태보다 큰 이그니션 전류 및 순시전력이 발생되고 있음을 알 수 있었다. 따라서 본 연구 결과는 전자식 안정기 설계 시, 특정 램프 뿐만 아니라 여러 램프의 이그니션 전류를 만족하는 설계가 필요하며, 메탈헬라이드 램프 시공 시, 램프의 이그니션 구간에서 발생하는 1-2[kV] 고전압 및 50[A] 이상의 대전류에 따른 적절한 안전사고 대책 및 관등회로의 절연, 전선 굵기 선정이 필요한 것으로 나타났다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.888-891
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• 2011

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping intensity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1047-1053
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• 2011

In this paper, we proposed an HF-band wireless power transfer system with adaptive frequency control circuit for efficiency enhancement in a short range. In general, a wireless power transfer system shows an impedance mismatching due to a reflected impedance, because a coupling coefficient is varied with respect to separation distance between two resonating loop antennas. The proposed method can compensate this impedance mismatching by varying input frequency of a voltage-controlled oscillator adaptively with respect to separation distance. Therefore, transmission efficiency is enhanced in a short distance, where large impedance mismatch occurs. The adaptive frequency circuit consists of a directional coupler, a detector, and a loop filter. In order to demonstrate the performance of the proposed system, a wireless power transfer system with adaptive frequency control circuits is designed and implemented, which has a pair of loop antennas with a dimension of 30${\times}$30 $cm^2$. From measured results, the proposed system shows enhanced efficiency performance than the case without adaptive frequency control.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.7
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• pp.829-835
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• 2010

This paper presents a disposable power generator for microfluidic devices; the power generator has a tubular PEMFC and a $H_2$ generator. The tubular PEMFC has a tubular MEA (diameter: 1.52 mm) that is supported by a spiral wire electrode. The $H_2$ generator supplied $H_2$ to the tubular PEMFC; $H_2$ was generated via the reaction of Al foil (27 mg) and 5 M NaOH (0.12 ml). The open circuit voltage and power density of a unit cell of the tubular PEMFC were 0.81 V and $16.4\;mW/cm^2$ (0.35 V), respectively. The $H_2$ generator generated 11.6 ml $H_2$ for 15min. The power generator was continuously operated for 15 min at 0.64 mW (0.71 V) and for 10 min at 1.06 mW (0.46 V). We experimentally verified that it is feasible to use the proposed power generator as a power source for microfluidic devices; in the experiment, an LED (2.5 mW; 1.8 V) was lit for 10 min by using three serially connected TPEMFCs and one $H_2$ generator.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.5
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• pp.44-51
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• 2008

UV lamp systems have been used for cleaning of display panels of TFT LCD or Plasma Display Panel (PDP). However, the needs for high efficient cleaning and low cost made high voltage plasma cleaning techniques to be developed and to be improved. Dielectric-Barrier Discharges (DBDs), also referred to as barrier discharges or silent discharges have been exclusively related to ozone generation for a long time. In this paper, a 6kW high voltage plasma power supply system was developed for LCD cleaning. The 3-phase input voltage is rectified and then inverter system is used to make a high frequency pulse train, which is rectified after passing through a high-power transformer. Finally, hi-directional high voltage pulse switching circuits are used to generate the high voltage plasma. Some experimental results showed the usefulness of atmospheric plasma for LCD panel cleaning.