• Proceedings of the KIPE Conference
• /
• 2014.07a
• /
• pp.239-240
• /
• 2014

본 논문에서는 국제 핵융합실험로용 VS 컨버터 제어기 해석 및 실험에 대하여 서술하였다. VS 컨버터는 플라즈마의 수직 안정성을 제어하기 위해서 ${\pm}1000V$의 정격전압과 최대 ${\pm}25kA$의 전류를 공급해야 하며, 영 전류구간이 없이 4상한 운전을 수행할 수 있어야 한다. 이를 위해서 부하전류의 크기에 따른 동작모드 구분과 순환전류제어기, 차전류 제어기가 요구되며 싸이리스터의 소자 특성에 의하여 발생하는 중복각 보상과 싸이리스터의 전류실패를 방지하는 감마제어가 포함이 된 점호각이 보장 되어야 한다. 본 논문에서는 국제 열핵융합실험로용 VS 컨버터 제어기를 해석하고, 실제 제어기와 RTDS를 연동하여 9ms의 순환전류 제어기 응답성과 계통에 50% 새그가 발생하였을 때 전류실패를 방지하는 감마제어의 타당성을 실험으로 확인하였다.

• Journal of IKEEE
• /
• v.26 no.2
• /
• pp.265-270
• /
• 2022

This paper proposes the detection algorithm for switch open fault of asymmetric 6-phase PMSM based on stationary reference frame dq-axis currents. In this paper, target motor has an asymmetric structure in which two upper three windings have an electrical phase difference of 30° and a neutral point is separated. As a result, dual 3-phase PWM inverters and the detection techniques due to open failures of switch are definitely required. In this paper, the dual dq-axis current control method is used for driving the asymmetric 6-phase PMSM and the open fault switch should be detected by using variable all pass filter and low pass filter in order to detect the current amplitude. The effectiveness and usefulness of the proposed method is verified by several experiments.

• Proceedings of the KIPE Conference
• /
• 2016.07a
• /
• pp.377-378
• /
• 2016

본 논문은 3상 인터리브드 양방향 DC-DC 컨버터의 전류 리플 최소화에 관한 것이다. 3상 양방향 컨버터를 부하에 따라 3상 또는 2상으로 상전환 시 전류 변동의 크기를 최소화하기 위한 스위칭 기법을 제안하고 시뮬레이션을 통하여 제안한 방식을 검증하였다.

• Proceedings of the KIPE Conference
• /
• 2012.07a
• /
• pp.526-527
• /
• 2012

본 논문은 상용계통의 전압에 불평형 및 왜곡이 있을 경우, 양방향 인버터의 동작에 영향을 주어 발생하는 계통전류의 불평형 및 왜곡을 보상해 주는 알고리즘을 제안한다. 일반적으로 3상 계통시스템은 공통 입력단자에 단상 부하 및 비선형 부하가 3상 부하와 같이 연결될 수 있으므로 종종 불평형과 왜곡이 발생한다. 이러한 불평형 및 왜곡상황에서 3상 양방향 인버터를 일반적인 방법으로 제어할 경우, 계통의 입 출력 전류의 불평형 및 왜곡 문제가 발생한다. 본 논문에서는 제어기 상에서 왜곡성분을 추출하고 이를 제어기의 출력에 보상하여 줌으로써 간단한 보상기법을 제시하며, 모의실험을 통하여 그 효과를 검증한다.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.7 no.4
• /
• pp.322-331
• /
• 2002

In this paper, a single-phase to three-phase PWM converter topology using a single-phase half-bridge PWM rectifier and a 2-leg inverter for low cost three-phase induction motor drives is proposed. In addition, the source voltage sensor is eliminated with a state observer which controls the deviation between the model current and the system current to be zero. The converter topology is of lower cost than the conventional one, which gives sinusoidal input current, unity power factor, dc output voltage control, bidirectional power flow and VVVF output voltage. The experimental results for V/F control of 3Hp induction motor drives have been shown.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.10 no.3
• /
• pp.365-373
• /
• 2015

The performance of 4-switch 3-phase inverter(FSTPI) is mainly affected by the unbalanced voltages between two capacitors which replace two switches of conventional 6-switch 3-phase inverter(SSTPI). This paper proposes a DC offset current injection method to compensate the capacitor voltage unbalance for FSTPI. A simplified SVPWM method which can be applied to FSTPI is also proposed. The validity of the proposed methods is verified by computer simulation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.6
• /
• pp.1291-1296
• /
• 2003

This paper deals with efficient diagnostic for stator winding fault of 3-phase induction motor using a current Park's vector approach. This method firstly transforms 3-phase stator current to vertical axis current and horizontal axis current of Park's Vector, and then obtains the each Park's Vector Pattern and detects stator winding fault by comparing to Park's Vector Pattern of healthy and fault. Experimental results, obtained by using induction motor having inter-turn fault of 2, 10, 20 turn, demonstrate the effectiveness of the proposed technique, for detecting the presence of stator winding fault under 25%, 50%, and 100% of full load condition.

• Journal of IKEEE
• /
• v.7 no.1 s.12
• /
• pp.56-62
• /
• 2003

In this paper, we designed a adder and a multiplier using current mode T-gate on $GF(2^2)$. The T-gate is consisted of current mirror and pass transistor, the designed 4-valued T-gate used adder and multiplier on $GF(2^2)$. We designed its under 1.5um CMOS standard technology. The unit current of the circuits is 15㎂, and power supply is 3.3V VDD. The proposed current mode CMOS operator have a advantage of module by T-gate`s arrangement, and so we easily implement multi-valued operator.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.18 no.3
• /
• pp.120-127
• /
• 2004

With the proliferation of nonlinear loads such as switching mode power supplies, high neurtral harmonic currents in three-phase four-wire distribution system have been observed. It has been known that the grounded impedance has an effect on the neutral current of a system which operates with harmonics present since the neutral conductor is grounded. On-site measurements of harmonic currents and voltages were made and the corresponding equivalent circuit was developed. The circuit model under study was simulated numerically and graphically through the use of the software MATLAB. Simulation results verifying the relationship between the neutral harmonic current and ground impedance are presented.

• Journal of the Microelectronics and Packaging Society
• /
• v.7 no.3
• /
• pp.27-29
• /
• 2000

For the DLC-coaled Si-tip FEA, the modified lift off-process, by which DLC coated on both gate electrode surface and gate insulator in the gate aperture could be removed, was proposed. In the process, the Al sacrificial layer was deposited on a tilted and rotated substrate by an e-beam evaporation, and DLC film was coated on the substrate by PA-CVD method. Afterward the DLC was perfectly removed except the DLC films coated on emitter tips by etch-out of Al sacrificial layer. Current-voltage curves and current fluctuation of the DLC-coated Si-tip FEA showed that the proposed lift-off process played an important role in decreasing gate leakage current and stabilizing omission current.