• Journal of Korea Society of Industrial Information Systems
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• v.15 no.1
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• pp.1-14
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• 2010

It is recently issued scalability, mobility and external internet connection on Wire-less sensor network. The low power wireless sensor networks based on IPv6 technology 6LoWPAN technology is being standardized in the IETF. This paper for the 6LoWPAN environment based on the routing protocol LOAD, route cost applied the packet re-transmission rate which follows in Link Qualities price which uses at course expense and packet transmission Minimum route Cost routing protocol where does on the course wherethe smallest packet re-transmission becomes accomplished proposed. The technique which proposes compared and LOAD and AODV that about 13%, about 16% energy consumption is few respectively averagely, Energy of the entire network equally, used and energy effectiveness and improvement of network life time experiment led and confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.