• Title/Summary/Keyword: 저전력 모드

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A study on the design exploration of Optical Image Stabilization (OIS) for Smart phone (스마트폰을 위한 광학식 손떨림 보정 설계 탐색에 관한 연구)

  • Lee, Seung-Kwon;Kong, Jin-Hyeung
    • Journal of Digital Contents Society
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    • v.19 no.8
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    • pp.1603-1615
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    • 2018
  • In order to achieve the low complexity and area, power in the design of Optical Image Stabilization (OIS) suitable for the smart phone, this paper presents the following design explorations, such as; optimization of gyroscope sampling rate, simple and accurate gyroscope filters, and reduced operating frequency of motion compensation, optimized bit width in ADC and DAC, evaluation of noise effects due to PWM driving. In experiments of gyroscope sampling frequencies, it is found that error values are unvaried in the frequency above 5KHz. The gyroscope filter is efficiently designed by combining the Fuzzy algorithm, to illustrate the reasonable compensation for the angle and phase errors. Further, in the PWM design, the power consumption of 2MHz driving is shown to decrease up to 50% with respect to the linear driving, and the imaging noises are reduced in the driving frequency above 2MHz driving frequency. The operating frequency could be reduced to 5KHz in controller and 10KHz in driver, respectively, in the motion compensation. For ADC and DAC, the optimized exploration experiments verify the minimum bit width of 11bits in ADC as well as 10bits in DAC without the performance degradation.

A Low-Power Current-Mode CMOS Voltage Reference Circuit (저전력 전류모드 CMOS 기준전압 발생 회로)

  • 권덕기;오원석
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1077-1080
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    • 1998
  • In this paper, a simple low-power current-mode CMOS wotage reference circuit is proposed. The reference circuit of enhancement-mode MOS transistors and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a threshold voltage. The designed circuit has been simulated using a $0.65\mu\textrm{m}$ n-well CMOS process parameters. The simulation results show that the reference circuit has a temperature coefficient less than $7.8ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.079%/V for a temperature range from $-30^{\circ}C$ to $130^{\circ}C$ and a VDD range from 4.0V to 12V. The power consumption is 105㎼ for VDD=5V and $T=30^{\circ}C.$ The proposed reference circuit can be designed to generate a wide range of reference voltages owing to its current-mode operation.

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An Energy Model for IEEE 802.11b based on Transmission Rate (전송률에 기반한 IEEE 802.l1b 에너지 모델)

  • 김태현;차호정
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10c
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    • pp.124-126
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    • 2004
  • 본 논문은 CAM(Constant Awake Mode), 및 PSM(Power Saving Mode)을 지원하는 IEEE 802.l1b[1] Infrastructure 환경에서 전송 프로토콜이 이동기기의 WNIC(Wireless Network Interface Card) 에너지 소비에 미치는 영향을 분석하고 단위 시간 동안 전송되는 데이터 양에 기반한 IEEE 802.l1b WNIC 에너지 모델을 제안한다. 제안하는 에너지 모델은 IEEE 802.l1b 환경에서 CAM 및 PSM 모드를 사용할때, 실제 측정한 값을 기반으로 설계되었다. 제안된 에너지 모델은 실험을 통하여 정확성을 검증하고, IEEE 802.l1b를 기반으로한 저전력 통신 관련 연구에서 시뮬레이션 시 사용 가능한 에너지 모델임을 밝힌다.

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Implementation of an Efficient Image Scaler for CMOS Image Sensor (CMOS 이미지 센서용 효과적인 이미지 스케일 구현)

  • Lee, Dong-Hun;Sonh, Seung-Il
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.2
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    • pp.307-310
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    • 2005
  • 본 논문은 CMOS 센서의 ISP 전처리 과정 후 최종 화면에 출력하기 위한 효과적인 이미지 스케일 블록을 저전력, 저비용에 맞은 독립된 하드웨어 장치로 설계 하고자 한다. 카메라 센서 이미지 결과를 디스플레이 장치(OSD(On Screen Display)에 맞는 화면의 크기는 CIF(352${\times}$288), QCIF(176${\times}$144) 출력 모드를 사용한다. 최근 DMB 휴대용 멀티미디어 데이터 전송 사이즈 포맷에서도 위와 같은 사이즈를 지원하고 있다. 일반적인 스케일 처리에서는 PC 그래픽 카드(Graphic Card)장치의 지원을 받아서 처리하는 경우가 많다. 또는 CPU의 연산을 통한 CPU 자원을 점유하여 이미지 스케일을 처리하였다. 휴대용 CMOS 센서용에 적합한 독립적으로 처리할 수 있는 이미지 스케일 기능을 하드웨어로 설계하여 효과적인 시스템 운용과 고속 이미지 스케일 처리가 가능한 하드웨어를 설계하는게 목적이다. 이를 구현 하기위해 기존 알고리즘과 제안한 알고리즘을 비교하여 최적화된 알고리즘 적용하여 VHDL설계언어를 이용한 하드웨어 설계 후, ModelSim 6.0a를 이용하여 데이터를 검증한다.

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An Area Efficient Low Pass Filter for Inner Hair Cell using CMOS Process (CMOS공정을 이용한 Inner Hair Cell의 모델링에 적합한 면적 효율적인 저역 통과필터의 설계)

  • Ryu, Seung-Tak;Lee, Kwang;Choi, Bae-Kun;Cho, Gyu-Hyeong
    • Proceedings of the KIEE Conference
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    • 2001.07d
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    • pp.2567-2569
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    • 2001
  • 본 논문에서는 내이(Inner ear)의 한 부분을 차지하는 Inner Hair Cell을 구현함에 있어 필수적인 요소인 낮은 극점을 갖는 저역통과필터(LPF)를 최소의 면적으로 구현하기 위한 설계방법을 언급한다. 이를 위해 본 논문에서는 CMOS Compatible Lateral BJT (CLBT)를 사용하여 능동소자의 등가 저항을 증가시켜 커패시터의 값을 획기적으로 줄일 수 있는 기법의 LPF와 gm-C필터를 이용한 LPF를 전류모드로 설계하였다. 저전력 특성과 큰 임피던스 특성을 얻기 위해 모든 트랜지스터는 약반전 영역에서 동작하고 극점은 1kHz근처에 존재한다.

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NIST 암호 표준화 공모전 동향

  • Kim, Hyeon-Jun;Park, Jae-Hun;Gwon, Hyeok-Dong;Seo, Hwa-Jeong
    • Review of KIISC
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    • v.30 no.6
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    • pp.117-123
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    • 2020
  • NIST에서는 앞으로 다가올 사물인터넷 환경과 양자 컴퓨터 시대를 대비하기 위해 2019년부터 경량암호 표준화 공모전을 그리고 2017년부터 양자내성암호 표준화 공모전을 각각 진행해 오고 있다. 경량암호 표준화 공모전은 경량 블록암호 운영 모드를 통해 저전력 사물인터넷 환경 상에서 높은 가용성을 만족하는 암호 개발을 그리고 양자내성암호 표준화 공모전은 양자컴퓨터 상에서의 양자알고리즘으로부터 안전한 공개키 암호 개발을 각각 목표로 하고 있다. 본 고에서는 차세대 암호의 표준화에 큰 영향을 미치게 될 NIST 경량암호 그리고 양자내성암호 표준화 공모전 동향을 상세히 확인해 보도록 한다.

Design of a Low-Power 8-bit 1-MS/s CMOS Asynchronous SAR ADC for Sensor Node Applications (센서 노드 응용을 위한 저전력 8비트 1MS/s CMOS 비동기 축차근사형 ADC 설계)

  • Jihun Son;Minseok Kim;Jimin Cheon
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.6
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    • pp.454-464
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    • 2023
  • This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

Design of Low-Power Hybrid LNA with Multi-Input for Mobile Ultrasound System (이동형 초음파시스템에 적합한 다중 입력방식의 저전력 혼성 저잡음 증폭기 설계)

  • Song, Jae-Yeol;Lee, Kyung-Hoon;Park, Sung-Mo
    • Journal of the Institute of Convergence Signal Processing
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    • v.15 no.2
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    • pp.64-69
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    • 2014
  • Ultrasound system is one of the complex wireless signal processing systems that are widely used in the fields of modern industry such as medical diagnostics, underwater communications, and sensor-networks. Miniaturization of ultrasound system has been raging recently. In this paper, a hybrid LNA that is suitable for miniaturization and mobile diagnostic ultrasound system has been developed. The proposed LNA has low noise figure of less than 5dB, and the feedback resistor is designed to be electrically adjusted in order to attain the impedance-matching for various ultrasound transducers. It supports the whole ultrasound frequencies from 10KHz to 150MHz frequency band and also provides sleep modes. A gain from -18.8 to -29.5 dB is achieved by adjusting each transducer to fit the system character. Power consumption can be reduced up to 90% in similar performance as compared to the existing LNA.

Design of Reassembly Unit Modular Wearable Device (단위 모듈 기반의 재조립 가능한 웨어러블 디바이스 구조 설계)

  • Lee, Geo-Yun;Kang, Soon-Ju
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.3
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    • pp.338-346
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    • 2016
  • Wearable Device has various constraint about battery power consumption, size, weight, etc, because the devices is worn and operated by person and provide services. So, if a device includes too many functions, it dose not satisfies the constraint and lose price competitiveness due to become expensive. Therefore we suggest that make reassembly Unit Modular Device witch has common used functions in wearable devices and user can receive various services to reassemble Unit Modules. It is comprised of frames and modules. Each module has various functions. Each frames help module to communicate each modules. To realize this device, we design to guarantee each services to use necessary modules, to give priority to modules depending on the important of the task, to set that does not use to low energy mode.

Development of Smart Etiquette System based on BLE and App (BLE 기반 스마트 에티켓 시스템 및 App 개발)

  • Hong, Seong-Pyo;Cho, Young-Ju
    • Journal of Digital Contents Society
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    • v.18 no.5
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    • pp.803-810
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    • 2017
  • Currently, every person possesses a smart phone due to the development of the IT industry. There is an improper situation in which a smart phone is not set in silent mode, such as a lecture room, a library, and a theatre hall. The proposed system automatically automates the function of smart phones where they are designated as a public place or etiquette area and automatically return the function of the smartphone if they deviate from the location of the site. It is also equipped with a combination of autonomous devices and services, based on Bluetooth communications, which are applied to ultra-light low-power IoT(Internet of Things) devices, and has features that allow diverse types of features and services to be added without requiring deformation of the hardware.