• Proceedings of the Korea Society for Simulation Conference
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• 1999.04a
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• pp.1-5
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• 1999

An ATM switch is the basic component of an ATM network, and its functioning is to switch incoming cells arriving at an input port to the output port associated with an appropriate virtual path. In case of an ATM switch with buffer sharing scheme, the performance analysis is very difficult due to the interactions between the address queues. In this paper, the influences of the degree of traffic burstiness and some traffic routing properties are investigated by using the simulation. Also, some cell access strategies including priority access and cell dropping are compared in terms of cell loss probability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1926-1940
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• 1998

This paper is the part II of research results on the performance evaluation of fully interconnected ATM switch, and includes the performance evaluation results for bursty traffic and nonuniform distribution. The switch model is a fyully interconnected switch type proposed by ETRI and is the proper architecutre for a small-sized switch element. The proposed switch consists of two steps of buffering scheme in the switch fabric in order to effectively absorb the effect of bursty nature of ATM traffic. The switch uses bit addressing method for addressing shcmeme and thus it is easy to implement multicasting function without adding additional functional block. In order to incorporate the bursty nature of traffic in ATM networks, we use IBP(Interrupted Bernoulli Process) model as an input traffic model as well as random traffic model which has been used as a traditional traffic model. In order to design the various scenarios for simulation, we considered both uniform and nonuniform output distribution, and also implemented multicast function. In this paper, we presented the simulation results in diverse environments and evaluated the performance of the switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.8
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• pp.1190-1200
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• 1993

In this work, the performance of both delay sensitive traffics and loss sensitive traffics of the output buffered ATM switch with priority control mechanisms has been evaluated. We choose the partial buffer sharing mechanism as the loss priority control mechanism and the HOL(Head Of Line) priority control mechanism as the time priority control mechanism. We model loss sensitive traffics with Poisson process and delay sensitive traffics with MMPP. With loss priority control, it is confirmed that loss probability of loss sensitive traffice decreases when the loss priority control mechanism is chosen. With time priority control, it has also been confirmed that mean cell delay of delay sensitive traffics decreases when the HOL priority control mechanism is used. From this analysis, It has been confirmed that the requirements of QOS for both loss sensitive and delay sensitive traffics can be satisfied in the ATM switch by combining both the loss priority control mechanism and the HOL priority control mechanism.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.223-226
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• 1998

In the Input Buffer Switch using the intial stage FIFO memory structure, It has pointed the Throughput limitation to the percent of 58.6 due to HOL(Head of Line) blocking in the DBP(Dedicated Buffer with Pointer) method, During that time, To overcome these problems, The prior papers have proposed the complicated Arbitration algorithms and Non-FIFO memory structures. and These showed the improved Throughput. But, Now, To design high speed ATM Switch which need to the tens of Giga bit/s or the tens of Tera bit/s. It has more difficulty in proceeding the priority of majority and the complicated Cell Scheduling, because of the problem in operating the control speed of the ratio of N to scanning each port and scheduling the Cell. In this paper, To overcome these problems, We could show more the improved performance than the existing DBP Window policy to design high speed ATM Switch.