• The KIPS Transactions:PartB
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• v.9B no.1
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• pp.83-90
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• 2002

In this work, an improved method of EZW is suggested for efficient compression and transmission of image data. Here, coding efficiency is accomplished by embedded coding of significant coefficients using lower-level insignificant coefficients, and coding time is decreased by pre-coding of lower-level coefficients in coefficient detection. In simulation of designed architecture, the performance improvement of 1dB PSNR is confirmed compared with the results by the original En method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.47-50
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• 2003

본 논문에서는 동영상을 효율적으로 부호화하기 위한 새로운 다중해상도 움직임 보상 방법과 잉여 양자화 방법을 제안한다. 본 논문에서 제안하는 동영상 부호화기는 다단계 이산웨이브렛 분해 움직임 예측 및 움직임 보상 블록 Tree 의 구성 및 블록 분할. 적응적 산술 부호화기로 구성된다 제안된 동영상 부호화기는 단순하면서도 낮은 연산량을 필요로 하며, 임베디드 특성과 SNR 계위 부호화 특성과 같은 좋은 기능을 제공한다. 또한 기존에 제안되었던 이산웨이브렛변환을 이용하는 동영상 부호화 방법과 비교하여 우수한 성능을 제공한다.

• Journal of Korea Multimedia Society
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• v.12 no.2
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• pp.200-208
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• 2009

JBIG2, as the next generation standard for binary image compression, must be designed in hardware modules for the JBIG2 FAX to be implemented in an embedded equipment. This paper proposes a hardware module of the high-speed Huffman coder for JBIG2. The Huffman coder of JBIG2 uses selectively 15 Huffman tables. As the Huffman coder is designed to use minimal data and have an efficient memory usage, high speed processing is possible. The designed Huffman coder is ported to Virtex-4 FPGA and co-operating with a software modules on the embedded development board using Microblaze core. The designed IP was successfully verified using the simulation function test and hardware-software co-operating test. Experimental results shows the processing time is 10 times faster than that of software only on embedded system, because of hardware design using an efficient memory usage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.182-192
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• 2010

This paper proposes the hardware IP design of JBIG2 encoder. In order to facilitate the next generation FAX after the standardization of JBIG2, major modules of JBIG2 encoder are designed and implemented, such as symbol extraction module, Huffman coder, MMR coder, and MQ coder. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the synthesis of VHDL code. To minimize the memory usage, 128 lines of input image are processed succesively instead of total image. The synthesized IPs are downloaded to Virtex-4 FX60 FPGA on ML410 development board. The four synthesized IPs utilize 36.7% of total slice of FPGA. Using Active-HDL tool, the generated IPs were verified showing normal operation. Compared with the software operation using microblaze cpu on ML410 board, the synthesized IPs are better in operation time. The improvement ratio of operation time between the synthesized IP and software is 17 times in case of symbol extraction IP, and 10 times in Huffman coder IP. MMR coder IP shows 6 times faster and MQ coder IP shows 2.2 times faster than software only operation. The synthesized H/W IP and S/W module cooperated to succeed in compressing the CCITT standard document.

• 전자공학회논문지 IE
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• v.43 no.1
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• pp.52-58
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• 2006

In order to provide an efficient way to processing with limited resources, we propose a wavelet coder that operates with little memory usage on the portable embedded system. In order to reduce redundancy in coding process caused by repetitive scanning of wavelet coefficients, the proposed coder uses a 2D significance coefficient array (SCA) which records the bit-level information of wavelet coefficients. The 2D SCA improves memory usage and processing speed required for image coding because it can perform significance check and bit coding of coefficients simultaneously.

• Journal of Broadcast Engineering
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• v.7 no.1
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• pp.37-44
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• 2002

In this paper. we propose a new video coding scheme with multi-resolution motion compensation and residual quantization. The main functional blocks of the proposed scheme include multi-level wavelet decomposition. motion estimation and motion compensation. raster scanning within each subband. formation of block trees and blocking partitioning. and adaptive arithmetic coding. Although the proposed ceding scheme is simple and requires low computational complexity, it produces bitstreams tilth good features. such as the embedded structure and SNR scalability. Experimental results demonstrate that the proposed coding scheme is quote competitive to and often outperforms other wavelet-based video coding schemes in the literature.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10C
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• pp.983-991
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• 2009

While H.264/AVC is in wide use for multimedia applications such as DMB and IPTV service, we have limited usage cases for embedded real-time applications due to its high computational demand. The paper provides judicious guide line for optimization method selection, by presenting the detailed experiments data through the development process of a real time H.264 software encoder on embedded DSP. The experimental analysis includes an intensive profiling analysis, fast algorithm application, optimal memory assignment, and intrinsic-based instruction selection. We have realized a real-time software that encodes CIF resolution videos 15 fps on TMS320DM64x processors.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.4
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• pp.198-205
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• 2002

In this paper, we proposed a wavelet image coder based on the portable embedded microprocessor. The proposed coder stores the bit level information of the wavelet coefficient in the 2D significance array. Using this information, the coder make the significance check for coefficient and bit level scanning at the same pass. The proposed method has the advantage that we can reduce the scan iteratively and the memory usage for the coding process. Experimental results show that the proposed method outperforms popular image coders such as JPEG, EZW and SPIHT in based on the portable embedded system environment.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.8
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• pp.48-54
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• 1999

A new method for wavelet embedded image coding is presented extending the bases of the Shapiro's algorithm by incorporating edge detection, zerotree scheme, and classified VQ(CVQ). Generally edges in the image are regarded an visually important components and the previous literatures have proved that significant coefficients in wavelet transform domain correspond to the edges in spatial domain. Hence, by identifying the edge elements, the significant coefficient can be easily detected in wavelet domain without investigating descendant coefficients across layer. Hierarchical trees for the significant components are organized, and then CVQ method is applied to these trees. Since the significant information has higher priority in transmission, the simulation shows that our coder provides a superior performance over the conventional method and can be successfully applied to the application areas that require of progressive transmission.