• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.5
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• pp.777-784
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• 2023

A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.

• Environmental engineer
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• v.24 s.247
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• pp.34-35
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• 2007

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.35-41
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• 2008

When memory devices are exposed to a space environment. they suffer various effects such as SEU(Single Event Upset). For these reasons, memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, the error detection and correction strategy in the Mass Memory Unit(MMU) of the STSAT-3 is discussed. The probability equation of un-recoverable SEUs in the mass memory system is derived when the whole memory is encoded and decoded by the RS(10,8) Reed-Solomon code. Also the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. The analyzed results can be used to determine the period of scrubbing the whole memory, which is one of the important parameters in the design of the MMU.

• Proceedings of the Korea Contents Association Conference
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• 2014.11a
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• pp.35-36
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• 2014

이 논문에서는 다수 노드로 구성되는 클러스터 환경을 위한 인-메모리 이동객체 분산 색인기법을 제안한다. 제안하는 방법은 Spark Stream의 D-strem모델을 사용하여 처리율 저하등의 문제를 유할 할 수 있는 잠금 기반의 동시성 제어방법을 배제한다.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.15 no.5
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• pp.125-133
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• 2016

Data processing capacity and speed are rapidly increasing due to the development of hardware and software in recent time. As a result, data usage is geometrically increasing and the amount of data which computers have to process has already exceeded five-thousand transaction per second. That is, the importance of Big Data is due to its 'real-time' and this makes it possible to analyze all the data in order to obtain accurate data at right time under any circumstances. Moreover, there are many researches about this as construction of smart factory with the application of Big Data is expected to have reduction in development, production, and quality management cost. In this paper, system using In-Memory Data Grid for high speed processing is implemented in semiconductor process which numerous data occur and improved performance is proven with experiments. Implemented system is expected to be possible to apply on not only the semiconductor but also any fields using Big Data and further researches will be made for possible application on other fields.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.826-828
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• 2004

XML은 기존의 HTML과 SGML의 단정을 보안한 마크업 언어로써, 큰 대역폭, 많은 메모리 양, 높은 CPU속도를 가지는 유선 환경에서부터 저 대역폭, 적은 메모리 양, 낮은 CPU속도를 가지는 모바일 장치까지 사용이 확대되어 지고 있다. 현재 모바일에서 사용되는 XML 파서중에서는 PULL 모델 기반 Kxml파서[1]만이 모바일 장치를 고려한 파서이다. 모바일 장치에서 XML의 많은 사용을 위해서는 저메모리를 사용하여 빠른 파서에 대한 연구가 필요하다. 본 논문에서는 piccolo 파서에서 사용한 Parser generator tool 인 JFlex를 사용하고, 파싱 모델 중 가장 빠르고 저 메모리를 사용하는 Pull 모델을 적용함으로써, 빠른 Token 추출과 이벤트 형 정의를 통해 좀더 빠른 XML 파서를 제안하고자 한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.450-450
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• 2013

플래시 메모리는 소형화가 용이하고, 낮은 구동 전압과 빠른 속도의 소자 장점을 가지기 때문에 휴대용 전자기기에 많이 사용되고 있다. 현재 사용되고 있는 플로팅 게이트를 이용한 플래시 메모리 소자는 비례축소에 의해 발생하는 단 채널 효과, 펀치스루 효과 및 소자 간 커플링 현상과 같은 문제로 소자의 크기를 줄이는데 한계가 있다. 이 문제를 해결하기 위해 FinFET, nanowire FET, 3차원 수직 구조와 같은 구조를 가진 플래시 메모리에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 비례축소의 용이함과 낮은 누설 전류의 장점을 가진 FinFET 구조를 가진 낸드 플래시 메모리의 전기적 특성에 대해 조사하였다. 메모리의 집적도를 높이기 위하여 비대칭 FinFET 구조를 가진 더블 게이트 낸드 플래시 메모리 소자를 제안하였다. 비대칭 FinFET 구조는 더블 게이트를 가진 낸드 플래시에서 각 게이트 간 간섭을 막기 위해 FinFET 구조의 도핑과 위치가 비대칭으로 구성되어 있다. 3차원 TCAD 시뮬레이션툴인 Sentaurus를 사용하여 이 소자의 동작특성을 시뮬레이션하였다. 낸드 플래시 메모리 소자의 게이트 절연 층으로는 high-k 절연 물질을 사용하였고 터널링 산화층의 두께는 두 게이트의 비대칭 구조를 위해 다르게 하였다. 두 게이트의 비대칭 구조를 위해 각 fin은 다른 농도로 인으로 도핑하였다. 각 게이트에 구동전압을 인가하여 멀티비트 소자를 구현하였고 각 구동마다 전류-전압 특성과 전하밀도, 전자의 이동도와 전기적 포텐셜을 계산하였다. 기존의 같은 게이트 크기를 가진 플로팅 게이트 플래시 메모리 소자에 비해 전류-전압곡선에서 subthreshold swing 값이 현저히 줄어들고 동작 상태 전류의 크기가 늘어나며 채널에서의 전자의 밀도와 이동도가 증가하여 소자의 성능이 향상됨을 확인하였다. 또한 양족 게이트의 구조를 비대칭으로 구성하여 멀티비트를 구현하면서 게이트 간 간섭을 최소화하여 각 구동 동작마다 성능차이가 크지 않음을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1325-1331
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• 1996

In this paper, a new current-memory circuit is proposed that reduces the clock feedthrough(CFT) error voltage causing total harmonic distortion(THD) increment in switched-current(SI) systems. Using PMOS transistor in CMOS complementary, the proposed one reduces output distortion current due to the CFT errorvoltage. A proposed current-memory is designed using a 1.2.mu.m CMOS process anda 1MHz sinusoidal signal having a 68.mu.A amplitude current is applied as input (sampling frequency:20MHz). It hasbeen shown from the simulation that the output distortion current effected by the CFT error voltage is reduced by approximately 10 times the error voltage of conventional one, THD is -57dB in case ofappling 1kHz frequency input signalwith 0.5 peak signal-to-bias current ratio.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.127-134
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• 2019

With the advancement of IT technology, the amount of data generated has been growing exponentially every year. As an alternative to this, research on distributed systems and in-memory based big data processing schemes has been actively underway. The processing power of traditional big data processing schemes enables big data to be processed as fast as the number of nodes and memory capacity increases. However, the increase in the number of nodes inevitably raises the frequency of failures in a big data infrastructure environment, and infrastructure management points and infrastructure operating costs also increase accordingly. In addition, the increase in memory capacity raises infrastructure costs for a node configuration. Therefore, this paper proposes an in-memory-based hybrid big data processing scheme for improve the big data processing rate. The proposed scheme reduces the number of nodes compared to traditional big data processing schemes based on distributed systems by adding a combiner step to a distributed system processing scheme and applying an in-memory based processing technology at that step. It decreases the big data processing time by approximately 22%. In the future, realistic performance evaluation in a big data infrastructure environment consisting of more nodes will be required for practical verification of the proposed scheme.