• Electronics and Telecommunications Trends
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• v.27 no.1
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• pp.51-60
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• 2012

실리콘 관통 홀(TSV) 기술은 2006년 삼성전자가 낸드 플래시 메모리에 적용하여 적층된 시제품을 선보인 이후 선풍적인 기술적 관심을 불러일으키고 있다. 그러나, 안타깝게도 CMOS 이미지 센서 모듈 외에는 실제로 양산에 적용되고 있는 사례가 매우 드물다. 이는 기술적으로, 그리고 상업적으로도 극복해야 하는 어려움이 많기 때문이다. 최근 Xilinx사는 28nm FPGA를 네 개의 작은 칩으로 분리하여 TSV가 있는 실리콘 인터포저 위에 2차원적으로 집적한 제품을 고객사들에게 선적하기 시작했다. 이와 같은 2.5D 집적 기술은 3D IC 집적 기술의 상용화를 위한 중간 단계로 여겨질 뿐만 아니라 그 자체로 독립적인 시장을 형성할 기술로도 판단되고 있다. 본고에서는 2.5D 집적을 위한 인터포저 기술개발 및 표준화 동향에 대해 소개하고자 한다.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.40-50
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• 2023

Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. For the s tacked PCB, it i s very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240℃ or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.3
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• pp.25-29
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• 2022

Recently, the importance of electronic packaging technology has been attracting attention, and heterogeneous integration technology in which chips are stacked out-of-plane direction is being applied to the electronic packaging field. The 2.5D integration circuit is a technology for stacking chips using an interposer including TSV, and is widely used already. Therefore, it is necessary to make the interposer mechanically reliable in the packaging process that undergoes various thermal processes and mechanical loadings. Considering the structural characteristics of the interposer on which several thin films are deposited, thermal stress due to the difference in thermal expansion coefficients of materials can have a great effect on reliability. In this study, the mechanical reliability of the metal pad for wire bonding on the silicon interposer against thermal stress was evaluated. After heating the interposer to the solder reflow temperature, the delamination of the metal pad that occurred during cooling was observed and the mechanism was investigated. In addition, it was confirmed that the high cooling rate and the defect caused by handling promote delamination of the metal pads.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.11-19
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• 2023

Recently with the rapid advancement of artificial intelligence (AI) technologies such as Chat GPT, AI semiconductors have become important. AI technologies require the ability to process large volumes of data quickly, as they perform tasks such as big data processing, deep learning, and algorithms. However, AI semiconductors encounter challenges with excessive power consumption and data bottlenecks during the processing of large-scale data. Thus, the latest packaging technologies are required for AI semiconductor computations. In this study, the authors have described packaging technologies applicable to AI semiconductors, including interposers, Through-Silicon-Via (TSV), bumping, Chiplet, and hybrid bonding. These technologies are expected to contribute to enhance the power efficiency and processing speed of AI semiconductors.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.11
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• pp.755-759
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• 2016

The use of heat pipes in the electronic telecommunication field is increasing. Among the various types of heat pipes, the thin flat heat pipe has relatively high applicability compared with the circular heat pipe in the electronic packaging application. The thin flat heat pipe based on extrusion fabrication has a simple capillary wick structure consisting of rectangular cross sectional grooves on the inner wall of the pipe. Although the groove serves as a simple capillary wick, and many such grooves are provided on the inner wall, it is difficult for the grooves to realize a sufficiently high capillary force. In the present study, a thin flat heat pipe with a wire bundle was developed to overcome the drawback of poor capillary force in the thin flat heat pipe with grooves, and was evaluated by conducting tests. In the performance test, the thin flat heat pipe with the wire bundle showed a lower thermal resistance of approximately 3.4 times, and a higher heat transfer rate of approximately 3.8 times with respect to the thin flat heat pipe with grooves as the capillary wick respectively. The possibility of using the wire bundle as a capillary wick in the heat pipe was validated in the present study; further study for commercializing this concept will be taken up in the future.