• Journal of KIISE:Computing Practices and Letters
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• v.14 no.1
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• pp.52-62
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• 2008

As various types of embedded devices are widely used, a technology that supports reuse of applications on multiple platforms is needed in order for time-to-market development of the applications. The interface middleware is one of such technology and it hides platform dependency from application programmers. Existing interface middleware such as the MT project, Xenomai and Legacy2linux have limitation in that the APIs provided by each of these middleware are fixed to a specific operating system, and the middleware does not provide dynamic expansion of its API set. In this paper, we propose a middleware which hides operating system dependencies and enables porting of applications on various operating systems. In addition, the middleware has scalable structure so that it is suitable for resource-limited embedded systems. The overhead of the middleware, i.e., the time delay occurred by the middleware is between $0.3{\mu}sec\;and\;5{\mu}sec$ in most cases. We believe that the amount of overhead is reasonable and does not hurt the performance of applications.

• Journal of KIISE:Software and Applications
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• v.30 no.5_6
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• pp.389-397
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• 2003

The component-based development methodology becomes famous as the new way for reuse. The goal of the reuse is improvement of quality, productivity and independence on the software development. For the improvement in the quality of a component-based system, it is necessary to research component metrics in the early phase of a component development. Hence, in this paper, we propose new component metrics using the information of a component analysis phase. Those are CCI(Complexity of Component Interface) and LCC(Lack Cohesion of Component interface). CCI indicates a difficulty about comprehension, modification, management, use of interface. LCC indicates a functional independence about how strong the elements are related with. Therefore, it is possible to predict and manage the quality of a component to be developed. Predicting a lowness of complexity and highness of cohesion as an independent functional unit by a component interface in the early phase of a component development, we can expect the improvement in the quality of a system.

• KIISE Transactions on Computing Practices
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• v.22 no.10
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• pp.488-496
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• 2016

In this paper, we introduce a virtual reality interface for scientific visualization applications. Our VR interface is based on an open-source framework called VR Juggler. Although VR Juggler has its own advantages, it lacks some of the important functionalities needed for practical applications - event handling, synchronization and data sharing among cluster nodes, to name a few. We explain how these issues are resolved while developing the VR interface. Also, a new interface with a smart device, which replaces the virtual reality input device, is introduced. Finally, system usability test results are provided to prove the effectiveness of the proposed interfaces.

• KIISE Transactions on Computing Practices
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• v.22 no.12
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• pp.632-645
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• 2016

The enterprise environment, various interface systems are utilized for business processes and for exchange of messages. In the interface communication environment, as business complexity increases, the interface system is connected with numerous systems. With increasing number of linked systems, there is a proportional increase in the workforce, leading to a rise in numerous risks (inconsistency of information, non-compliance with standards, etc.). To solve the problem, we propose a system for managing and centralizing information of the message based interface system. The proposed system enables information integration management, message information distribution, standard code generation, risk management and risk evasion. Using the proposed system, the in development environment user can prevent inconsistent information, analyze risk, avoid risk, distribute information automatically and create a standard code. Ultimately, there is an increase in user productivity and it is possible to evade the risks involved.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.5
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• pp.498-508
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• 2003

In the field of finance, Trading System of Securities is a very vulnerable application when it faces any small problems just for one minute. Since Trading System changes its environment from mainframes to client/server, its safety becomes the most important factor. Even though most If systems are configured by general guidelines currently, Trading System is an exception that it is configured by specific and rather ad hoc guidelines in order to ensure its safe management. In this thesis, I will prove the validity of specific and ad hoc configuration in the environment of Trading Systems where I use both XA interface system and Non-XA interface to configure its system based on 3-Tier Client/server computing environment through middleware, TP-Monitor, in the X/Open DTP Model. In order to validate the Trading System, I will compare and analyze the error of data of an order and ability to restore using both XA and Non-XA interfaces while testing take-over scenario on the assumption of the system's failure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.302-312
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• 2001

As the data transfer rate between chips gets higher, both crosstalk and SSN (Simultaneous Switching Noise) deteriorate seriously the performance of a system. The proposed interface scheme uses P-CTR and N-CTR(Positive/Negative Constant Transition Rate) which encodes data at both falling and rising edges, where the transition directions of N-CTR and P-CTR are opposite. And the proposed bus system places two P-CTR drivers and two N-CTR drivers alternatively. In the proposed P/N-CTR interface scheme, the signals of neighboring interconnection lines at both sides of a bus will not switch simultaneously in the same direction, which leads to reduction in the maximum crosstalk and SSN compared to conventional interfaces. For verification of noise reduction of the proposed interface scheme, the scheme is applied to several kinds of bit-wide buses with various interconnection structures, and HSPICE simulation was performed with 0.35 ${\mu}{\textrm}{m}$ SPICE parameters. The simulation results show that in the 32-bit or less wide bus, the maximum SSN and crosstalk are reduced to at least 26.78% and 50%, respectively in comparison with the conventional interface scheme.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.323-339
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• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.48-55
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• 1999

This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the AGC in the proposed system is controlled directly by digital bits without conventional extra D/A converters and the signal settling behavior is almost independent of AGC gain variation at video speeds. A capacitor-segment combination technique to obtain large capacitance values considerably improves the effective bandwidth of the AGC based on switched-capacitor techniques. A proposed layout scheme for capacitor implementation shows AGC matching accuracy better than 0.1 %. The outputs from the AGC are transferred to a 10b A/D converter integrated on the same chip. The proposed AGC is implemented as a sub-block of a CCD camera interface system using a 0.5 um n-well CMOS process. The prototype shows the 32-dB AGC dynamic range in 1/8-dB steps with 173 mW at 3 V and 25 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.412-415
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• 2015

This paper presents a MPPT(Maximum Power Point Tracking) control CMOS interface circuit for vibration energy harvesting. The proposed circuit consists of an AC-DC converter, MPPT Controller, DC-DC boost converter and PMU(Power Management Unit). The AC-DC converter rectifies the AC signals from vibration devices(PZT). MPPT controller is employed to harvest the maximum power from the PZT and increase efficiency of overall system. The DC-DC boost converter generates a boosted and regulated output at a predefined level and provides energy to load using PMU. A full-wave rectifier using active diodes is used as the AC-DC converter for high efficiency, and a schottky diode type DC-DC boost converter is used for a simple control circuitry. The proposed circuit has been designed in a 0.35um CMOS process. The chip area is $950um{\times}920um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.547-550
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• 2009

This paper presents a digital based input/output interface circuit for controlling and monitoring the Diesel Engine Generator for Emergency. In order to monitor and control of the Emergency Diesel Engine Generator, controlling and monitoring circuits need 5 analog input channels, 2 pick-up coil measuring circuits, 10 digital input channels containing Broken Wire Detect function, and 7 relay control signal output channels. This system performs signal processing of input signal taking advantage of simple filter circuit, photo-coupler and comparator circuit at analog input parts, and output signals for main relay is designed acting by double control, so it prevents malfunction completely. And it improves accuracy of speed input signal by applying digital circuit that processes pick-up coil signal.