• Journal of Elementary Mathematics Education in Korea
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• v.14 no.2
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• pp.241-262
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• 2010

This study was carried out to identify the cognitive obstacles while using addition and subtraction with fractions, and to analyze the sources of cognitive obstacles. For this purpose, the following research questions were established : 1. What errors do elementary students make while performing the operations with fractions, and what cognitive obstacles do they have? 2. What sources cause the cognitive obstacles to occur? The results obtained in this study were as follows : First, the student's cognitive obstacles were classified as those operating with same denominators, different denominators, and both. Some common cognitive obstacles that occurred when operating with same denominators and with different denominators were: the students would use division instead of addition and subtraction to solve their problems, when adding fractions, the students would make a natural number as their answer, the students incorporated different solving methods when working with improper fractions, as well as, making errors when reducing fractions. Cognitive obstacles in operating with same denominators were: adding the natural number to the numerator, subtracting the small number from the big number without carrying over, and making errors when doing so. Cognitive obstacles while operating with different denominators were their understanding of how to work with the denominators and numerators, and they made errors when reducing fractions to common denominators. Second, the factors that affected these cognitive obstacles were classified as epistemological factors, psychological factors, and didactical factors. The epistemological factors that affected the cognitive obstacles when using addition and subtraction with fractions were focused on hasty generalizations, intuition, linguistic representation, portions. The psychological factors that affected the cognitive obstacles were focused on instrumental understanding, notion image, obsession with operation of natural numbers, and constraint satisfaction.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.769-772
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• 2001

Waish-Hadamard Transform은 압축, 필터링, 코드 디자인 등 다양한 이미지처리 분야에 응용되어왔다. 이러한 Hadamard Transform을 기본으로 확장한 Jacket Transform은 행렬의 원소에 가중치를 부여함으로써 Weighted Hadamard Matrix라고 한다. Jacket Matrix의 cocyclic한 특성은 암호화, 정보이론, TCM 등 더욱 다양한 응용분야를 가질 수 있고, Space Time Code에서 대역효율, 전력면에서도 효율적인 특성을 나타낸다 [6],[7]. 본 논문에서는 Distributed Arithmetic(DA) 구조를 이용하여 Fast Jacket Transform(FJT)을 구현한다. Distributed Arithmetic은 ROM과 어큐뮬레이터를 이용하고, Jacket Watrix의 행렬을 분할하고 간략화하여 구현함으로써 하드웨어의 복잡도를 줄이고 기존의 시스톨릭한 구조보다 면적의 이득을 얻을 수 있다. 이 방법은 수학적으로 간단할 뿐 만 아니라 행렬의 곱의 형태를 단지 덧셈과 뺄셈의 형태로 나타냄으로써 하드웨어로 쉽게 구현할 수 있다. 이 구조는 입력데이타의 워드길이가 n일 때, O(2n)의 계산 복잡도를 가지므로 기존의 시스톨릭한 구조와 비교하여 더 적은 면적을 필요로 하고 FPGA로의 구현에도 적절하다.

• Journal of the Korea Society of Computer and Information
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• v.19 no.10
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• pp.55-62
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• 2014

In the intelligent video surveillance system, moving objects generally are detected by calculating difference between background and input image. However formation of reliable background is known to be still challenging task because it is hard to cope with the complicated background. In this paper we propose an adaptive background formation algorithm considering stationary object. At first, the initial background is formed by averaging the initial N frames. Object detection is performed by comparing the current input image and background. If the object is at a stop for a long time, we consider the object as stationary object and background is replaced with the stationary object. On the other hand, if the object is a moving object, the pixels in the object are not reflected for background modification. Because the proposed algorithm considers gradual illuminance change, slow moving object and stationary object, we can form background adaptively and robustly which has been shown by experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.85-92
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• 2009

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.