• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.3
• /
• pp.269-281
• /
• 2014

In this paper, a systematic design of a low phase noise voltage-tuned dielectric resonator oscillator(VTDRO) using loop group delay is proposed. Designed VTDRO is closed-loop type and consists of a cascade connection of a resonator, phase shifter, and amplifier. Firstly, a reference VTDRO is fabricated and its phase noise and electrical frequency tuning range are measured. Both the phase noise and electrical frequency tuning range depend on the loop group delay. Then, a required value of loop group delay for a new VTDRO with a low phase noise can be systematically computed. In addition, its phase noise and electrical frequency tuning range can be theoretically estimated using those obtained from the measurement of the reference VTDRO. When the loop group delay increases, the phase noise decreases and the electrical frequency tuning range also decreases. The former predominantly depends on the resonator structure. Therefore we propose a systematic design procedure of a resonator with high group delay characteristics. The measured loop group delay of the new VTDRO is about 700 nsec. The measured phase noise of the new VTDRO show a state-of-the-art performance of 154.5 dBc/Hz at 100 kHz frequency offset and electrical frequency tuning range of 448 kHz for a voltage change of 0~10V. The oscillation power is about 4.39 dBm.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.4
• /
• pp.683-690
• /
• 2018

In this paper, a new signal processing technique is proposed for calibrating gain, phase, delay offsets in array antenna based anti-jamming minimum variance distortionless response (MVDR) global-positioning-system (GPS) receivers. The proposed technique estimates gain, phase and delay offsets across the antennas, and compensates for the offsets based on the estimates. A pilot signal with good correlation characteristics is used for accurate estimation of the gain, phase and delay offsets. Based on the cross-correlation, the delay offset is first estimated and then gain/phase offsets are estimated. For fine delay offset estimation and compensation, an interpolation technique is used, and specifically, the discrete Fourier transform (DFT) is employed for the interpolation technique to reduce the computational complexity. The proposed technique is verified through computer simulation using MATLAB. According to the simulation results, the proposed technique can reduce the gain, phaes and delay offset to 0.01 dB, 0.05 degree, and 0.5 ns, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.10A
• /
• pp.969-979
• /
• 2002

This paper proposes an novel method of minimizing Interference which causes data decision error in digital wireless communications. In this method, in order to suppress ISI which is caused by the phase difference between the transmitted and received signal phases, the transmitted and received signals are always kept orthogonal by compensating the transmitted signal for detecting the phase noise and the delay of the received signal was implemented by MOS circuits. To delay the phase of the signal, additive white Gaussian noise (AWGN) environment was used. The phase and delay of the signal transmitted through AWGN channel were compensated in the modulator of the transmitter and the compensated signal was demodulated using quasi-direct conversion receiver and QPSK demodulator. ISI suppression was achieved by keeping the orthogonality between the compensated transmitted signal and the receive signal. The error probability of data decision was compared. By simulation the proposed system was proved to be effective in minimizing the ISI.

• Journal of IKEEE
• /
• v.10 no.1 s.18
• /
• pp.16-21
• /
• 2006

This paper shows a vernier delay technique for generating precise multiphase clocks using PLL structure. The proposed technique can achieve the finer timing resolution less than the gate delay of the delay chain in VCO. Using this technique, 62.5ps of timing resolution can be achieved if the reference clock rate is set at 1GHz using 0.18um CMOS technology. Jitter of 14ps peak-to-peak was measured.

• Proceedings of the KIPE Conference
• /
• 2014.11a
• /
• pp.41-43
• /
• 2014

본 논문은 전류모델과 전압모델의 장점을 취해 자속을 추정하는 고피나스(Gopinath) 모델 자속 추정기에 속도 피드백 오차가 미치는 영향에 대해 분석하였다. 속도 오차는 전류 모델의 위상 지연 및 크기 오차를 발생시키고, 이로 인해 고피나스 모델에 의해 추정 된 회전자 자속의 위상 및 크기에 오차가 발생하였다. 따라서 전류모델에 발생한 위상 지연을 통해 속도 오차를 보상하여 자속 추정 오차를 감소시키는 새로운 알고리즘을 제시하였고, 시뮬레이션 결과를 통해 검증하였다.

• Electronics and Telecommunications Trends
• /
• v.9 no.1
• /
• pp.1-10
• /
• 1994

본 고에서는 전화망에서 발생되는 여러 전송 장애 요인들이 팩시밀리 통신에서 화상에 어떤 영향을 주는지 각 파라미터에 대하여 측정하였다. 이 연구에서 선정된 주요 파라미터는 최근의 측정 결과를 바탕으로 하였다. 이러한 파라미터들은 전송 선로의 특성에 따른 감쇠 왜곡, 군지연 왜곡 등과 그 외에 임펄스성 잡음, 위상지연, 위상 히트 등이다. 이 파라미터들은 모두 팩시밀리 화상 품질에 영향을 주고 있으므로 일정 수준의 팩시밀리 품질을 유지하기 위해서는 영향을 주는 파라미터를 관리하여야 한다.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.11 no.4
• /
• pp.365-372
• /
• 2016

Recently, UWAC(: UnderWater Acoustic Communication) has been studied by many scholars and researchers. There are several method to estimate the time-difference between the two signals such estimating as the arrival time of the first non-background segment in both signals and calculate the temporal difference, calculating the cross-correlation between the two signal to infer the time-lagged, and estimating the phase delay to infer the time difference. In this paper, we present estimating method by the phase delay to infer the time difference in two signals.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.1
• /
• pp.137-144
• /
• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.

• Korean Journal of Optics and Photonics
• /
• v.18 no.2
• /
• pp.162-166
• /
• 2007

In this paper, we propose a WDM optical true time-delay (OTTD) beam former for phased way antenna (PAA) systems. It is composed of a delay lines matrix and a multiwavelength source with discrete DFB laser diodes. The building block of a delay lines matrix is a $2\times2$ optical MEMS switch with proper fiber-optic delay line connected between cross ports. A $4\times3$ matrix using four DFB lasers has been fabricated with unit time-delay difference of 12 ps. Maximum time-delay error was measured to be -1.74 ps and +1.14 ps at a radiation angle of $46.05^{\circ}$, corresponding to error range of $-2.87^{\circ}\sim+1.88^{\circ}$. By measuring time-delays at six different RF frequencies from 5- to 10-GHz, we verified the true time-delay characteristic of our OTTD.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.6
• /
• pp.1199-1206
• /
• 2018

The hybrid phase shifting device is consist of general phase shifter in sub-array and the true time delay inter sub-array. This configuration for phased shifting can efficiently improve the beam squint according to frequencies. However, when an appropriate array configuration is not selected, a gain variation of main lobe for a phased array antenna is occurred. In order to solve these problems, a simplified formula for constructing efficient array based on the system design requirements, such as the fractional bandwidth, the maximum beam steering angle, and limit criterion of the gain variation, was presented.