• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10A
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• pp.969-979
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• 2002

This paper proposes an novel method of minimizing Interference which causes data decision error in digital wireless communications. In this method, in order to suppress ISI which is caused by the phase difference between the transmitted and received signal phases, the transmitted and received signals are always kept orthogonal by compensating the transmitted signal for detecting the phase noise and the delay of the received signal was implemented by MOS circuits. To delay the phase of the signal, additive white Gaussian noise (AWGN) environment was used. The phase and delay of the signal transmitted through AWGN channel were compensated in the modulator of the transmitter and the compensated signal was demodulated using quasi-direct conversion receiver and QPSK demodulator. ISI suppression was achieved by keeping the orthogonality between the compensated transmitted signal and the receive signal. The error probability of data decision was compared. By simulation the proposed system was proved to be effective in minimizing the ISI.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.46-52
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• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.1
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• pp.47-55
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• 1994

This paper investigates the performance analysis of the packet DS/SS receiver with a PJED(phase-jump error detector) using the block signal processing(BSP) methods. The conventional packet DS/SS block receiver has a high probability of mistaking the phase-jump detection, which causes the frequency estimation error. The conventional receiver uses a Matched-Pulse Timing Extractor which has a complicated structure. The proposed packet DS/SS block receiver with the PJED which uses libearity of the phase has little probability of mistaking the phase-jump detection. The proposed Matched Pulse Timing Extractor gas the more simple structure but obtains the same performance on the exact matched-pluse timing as the conventional one does. The simulation results show that the proposed receiver gives about 2dB improvement in the BER compared with the conventional receiver.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.305-308
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• 2007

본 논문에서는 전력품질 향상용 전력전자기기의 제어에 중요한 정보인 전원의 위상각을 검출하는 기존의 방법들에 대해서 먼저 알아보고, 그 중 불평형한 전원단 전압조건에서도 정확한 위상각을 검출할 수 있는 전차원 상태관측기를 이용한 정상분 전압 추출 PLL(Phase Locked Loop) 방법을 제안한다. 제안된 PLL 방법은 기존의 전역 통과 필터(APF, All Pass Filter)를 이용한 정상분 전압추출기 대신 전차원 상태관측기를 사용함으로써 불평형사고 발생 시 과도상태 응답특성을 개선하였다. 기존의 정상분 전압 추출 PLL 방법과 본 논문에서 제안된 PLL 방법의 성능을 비교하기 위해, 전원단 전압에 불평형 사고 발생시 위상각을 검출하는 모의실험과 실험을 하였고, 이를 통해 기존의 전역 통과 필터를 이용한 정상분 전압 추출 PLL 방법보다 제안된 전차원 상태관측기를 이용한 정상분 전압 추출 PLL 방법의 과도상태 응답특성이 개선됨을 입증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.34-40
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• 2002

In this paper, a new encryption method for a binary image using Phase modulation and Fourier transform is proposed. For decryption we use the characteristics of square law detector. In encryption process, a key image is obtained by phase modulation of 256 level random pattern and its Fourier transformation, and input image is encrypted by Fourier transforming the multiplication of the phase modulated random pattern and phase modulated input image. The encrypted image and key image have only phase information, so they can not be copied or counterfeited and the original image can not be decrypted without the key image. To reconstruct the original image, each phase mask of the key image and the encrypted image must be placed on each path of the Mach-Zehnder interferometry with Fourier transform lens and the output image is obtained in the form of intensity in the CCD(Charge Coupled Device) camera. The real-time decryption is possible in the proposed system by use of a LCD as a phase modulator and a CCD camera as an intensity detector. The proposed method shows a good performance in the computer simulation and optical experiment as an encryption scheme.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.773-782
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• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.6
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• pp.816-824
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• 1999

Design and performance of 18 GHz phase locked dielectric resonator oscillator(PLDRO) for Point-to-point radio link using analog phase locked loop is described which achieve high stability and low SSB phase noise. The module consists of an 18 GHz voltage controlled dielectric resonator oscillator(VCDRO), buffered amplifier, analog phase detector which are integrated to form a miniature hybrid circuit. In addition, containing a low phase noise VHF PLL has been designed to lock any other conventional N times frequency of crystal oscillator. The module achieves stable phase locked state, exhibits output power of 21 dBm at 18.00 GHz, -34 dBc harmonic suppression and -75 dBc/Hz phase noise at 10 kHz offset frequency from carrier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.2
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• pp.168-180
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• 1992

Commumication technology has been continuously developed to overcome the distance and time for the transmission of information to the human society. Wireless mobile communication, which had been used mostly in the military and police is widely used these days for enterprise and individuals. Therefore the domestic usage of the advanced mobile phone service are progressively gaining wide popularity. The modulation techniques used usually in mobile communications were the analog techniques such as AM and FM, but they are getting replaced by the digital techniques, However, the major disadvantage of the digital communications is the increase of the transmission bandwidth. Therefore, it is very important to use efficiently the limited frequency bandwidth. The domestic research and development on the subject seems quite limited and in order to establish the technology of the digital mobile communications. This thesis presents the design of the frequency hopping synthesizer providing 124 channels with a channel spcing of 200KHz. VCD used in the synthesizer employs a semi-rigid cable for higher purity of signal spectrum, and a hybrid pgase detector is realized with a sample hold phase detector in conjuction with a tri-state phase detedctor.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.448-452
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• 2007

본 논문은 선박의 축계마력 측정방법 및 측정시스템의 개발방법에 대해 논의한다. 엔진 축계에서의 정확한 출력은 선박의 사용목적, 관련추진축계의 제작 및 설치비용 등과 밀접한 관련을 맺고 있다. 본 연구에서는 동력 전달측과 부하측사이의 축상에 두 개의 기어휠을 설치하고 각각의 기어휠에 비접촉식 검출기를 부착하여 위상을 계측한다. 동력이 가해질 경우 두 지점에서는 비틀림 각에 의한 위상차가 발생하게 되고, 발생된 위상차를 전압신호로 검출하여 축에서의 마력을 계산하게 된다.