• Title/Summary/Keyword: 요소 기반 시뮬레이션

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An Experimental Study on Real Time CO Concentration Measurement of Combustion Gas in LPG/Air Flame Using TDLAS (TDLAS를 이용한 LPG/공기 화염 연소가스의 실시간 CO 농도 측정에 관한 연구)

  • So, Sunghyun;Park, Daegeun;Park, Jiyeon;Song, Aran;Jeong, Nakwon;Yoo, Miyeon;Hwang, Jungho;Lee, Changyeop
    • Clean Technology
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    • v.25 no.4
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    • pp.316-323
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    • 2019
  • In order to enhance combustion efficiency and reduce atmosphere pollutants, it is essential to measure carbon monoxide (CO) concentration precisely in combustion exhaust. CO is the important gas species regarding pollutant emission and incomplete combustion because it can trade off with NOx and increase rapidly when incomplete combustion occurs. In the case of a steel annealing system, CO is generated intentionally to maintain the deoxidation atmosphere. However, it is difficult to measure the CO concentration in a combustion environment in real-time, because of unsteady combustion reactions and harsh environment. Tunable Diode Laser Absorption Spectroscopy (TDLAS), which is an optical measurement method, is highly attractive for measuring the concentration of certain gas species, temperature, velocity, and pressure in a combustion environment. TDLAS has several advantages such as sensitive, non-invasive, and fast response, and in-situ measurement capability. In this study, a combustion system is designed to control the equivalence ratio. Also, the combustion exhaust gases are produced in a Liquefied Petroleum Gas (LPG)/air flame. Measurement of CO concentration according to the change of equivalence ratio is confirmed through TDLAS method and compared with the simulation based on Voigt function. In order to measure the CO concentration without interference from other combustion products, a near-infrared laser at 4300.6 cm-1 was selected.

Performance Analysis of Slave-Side Arbitration Schemes for the Multi-Layer AHB BusMatrix (ML-AHB 버스 매트릭스를 위한 슬레이브 중심 중재 방식의 성능 분석)

  • Hwang, Soo-Yun;Park, Hyeong-Jun;Jhang, Kyoung-Son
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.5_6
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    • pp.257-266
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    • 2007
  • In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.