• Transactions of the Korean Society of Mechanical Engineers A
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• v.21 no.12
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• pp.2146-2155
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• 1997

This paper presents the Wire Parallel Mechanism for robot pose measurement which can be used to robot calibration. It is constructed with six parallel links using wire. The position and orientation of the end effector of a robot are calculated from the wire length that measured by the encoder. The unique solution is obtained from a Newton-Raphson method and geometric configuration of the mechanism, also the method to estimate a measuring space is presented. Through the simulations, it is verified that the proposed mechanism can measure a robot pose, and has a large measuring space. In conclusion, it can be used effectively in a robot pose measurement with little cost and effort.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.5
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• pp.134-142
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• 1997

In this study, we proposed the wire parallel mechanism that can be used to measure a full pose of a robot. It is composed of six parallel links using wire. The position and orientation of the end effectorf of a robot are calculated using the length of wires which is measured by the encoder. The complex non- linear equations of the forward kinematics are solved by using a numerical method, and the unique solution is obtained from the geometric configuration of the device. The length error of the wire which occurs in static condition is compensated by the relational equation that considered longitudinal extension and defoection of the wire. Through this work, we known that the proposed device has a good accuracy( .+-. 0.01mm) in a large measuring region, so it can be used effectively in a callibration of a robot which required a low cost.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.118-126
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• 1996

Memory hierarchy is a useful mechanism for improving the memory access speed and making the program space larger by layering the memories and separating program spaces from memory spaces. However, it needs at least two memory accesses for each data reference : a TLB(Translation Lookaside Buffer) access for the address translation and a data cache access for the desired data. If the cache size increases to the multiplication of page size and the cache associativity, it is difficult to access the TLB with the cache in parallel, thereby making longer the critical timing path in the processor. To achieve such parallel accesses, we present the hybrid mapped TLB which combines a direct mapped TLB with a very small fully-associative mapped TLB. The former can reduce the TLB access time. while the latter removes the conflict misses from the former. The trace-driven simulation shows that under given workloads the proposed TLB is effective even when a fully-associative mapped TLB with only four entries is added because the effects of its increased misses are offset by its speed benefits.