• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2000.05a
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• pp.51-52
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• 2000

전기아연도금강판은 표면이 미려하고 희생방식력이 뛰어나기 때문에 주로 자동차와 가전, 건자재 등에 많이 사용된다. 현재 냉연 표면처리 제품들은 연속도금공정에 의해 생산되고 있으며 고전류밀도에 의한 고속생산과 도늠액 제조와 조성이 비교적 단순해야 하는 여러 가지 이유로 염산욕과 황산욕을 가장 많이 사용하고 있다. 최근에 신설된 당사의 전기도금공정은 수직형으로 황산욕에서 불용성 양극을 채용하여 아연을 전기도금하고 있다. 일반적으로 황산욕은 염산욕 대비 전기 전도성이 나빠 과전압이 크게 걸리므로 불용성 양극을 사용하여 극간 거리를 최소화할 필요가 있다. 그러나 $Ir0_2$가 코팅된 불용성 양극은 가격이 비싸기 때문에 극간 거리를 너무 짧게 하면 깡대에 의해 손상을 받을 수가 있어 극간 거리를 줄이는데 한제가 있다. 따리서 용액의 전도도들 증가시켜 과전합을 줄이기 위해서는 타사에서 현재 사용하고 있는 황산나트륨, 황산칼륨, 황산암모늄 등에 대한 검토가 필요하다. 전기전도 보조제들은 용액의 전기전도도 뿐만 아니라 도금층의 외관 및 미세구조에도 많은 영향을 주는 것으로 알려져 있다. 따라서 본 연구에서는 황산나트륨, 황산암모늄의 농도를 변화시켜 표면외관, 한계전류밀도, 미세구조, 우선배향성 등을 조사하여 최적의 물성을 갖는 아연 도금층을 얻기 위한 조건을 도출하고자 하였다. 전기아연도금용 소재로는 두께 0.8mm이고 크기가 $100{\times}120mm$인 중저탄소강 (0.02% C)을 사용하였으며 전처리 과정으로 탈지와 산세를 행하고 현장 도금액을 사용하여 다음과 같은 조건 하에서 아연도금을 행하였고 극간전합을 측정하였다. 도금 후 표면의 미세구조는 SEM을 사용하여 관찰하였으며 표면외관 특성을 분석하기 위해 광택도계(Tri- Microgloss-60-85)를 이용하여 입사각 $60^{\circ}$ 에서 광택도를 측정하였고, 색차계(Color Quest II Hunter Lab.)를 사용하여 백색도를 각각 측정하였다. 또한 X선 회절기를 이용하여 도금층의 우선 배향성을 분석하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.