• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.8
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• pp.1-11
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• 2012

The multi-code spread spectrum communication system, which spreads data bit stream by multiplexing orthogonal codes, can transmit data in high rate. However it needs the high-cost good linear amplifier because of the multi-level output signal. In order to overcome this drawback several systems making the amplitude of output signal constant with Walsh codes have been proposed. Recently constant amplitude pre-coded multi-code spread spectrum systems using extended m-sequence have been proposed. In this paper we consider an extended m-sequence based constant amplitude multi-code spread spectrum system with code set partitioning. By grouping the orthogonal codes into 4 subsets, not only is the computational complexity of the transceiver reduced but BER performance also improves. It has been shown that parity checking on four detected codes at the receiver can correct code detection error and result in BER performance enhancement. In this paper we propose a improved parity check receiver. We carried out computer simulation to verify feasibility of the proposed algorithm.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.1
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• pp.29-38
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• 2012

Due to the rapid development of network environment and wireless communication technology, the distribution of digital video has made easily and the importance of the protection for digital video has been increased. This paper proposes the digital video encryption system based on multiple chaos maps for MPEG-2 video encoding process. The proposed method generates secret hash key of having 128-bit characteristics from hash chain using Tent map as a basic block and generates $8{\times}8$ lattice cipher by applying this hash key to Logistic map and Henon map. The method can reduce the encryption overhead by doing selective XOR operations between $8{\times}8$ lattice cipher and some coefficient of low frequency in DCT block and it provides simple and randomness characteristic because it uses the architecture of combining chaos maps. Experimental results show that PSNR of the proposed method is less than or equal to 12 dB with respect to encrypted video, the time change ratio, compression ratio of the proposed method are 2%, 0.4%, respectively so that it provides good performance in visual security and can be applied in real time.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.153-164
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• 2010

A program consumes energy by executing its instructions. The amount of cosumed power is mainly proportional to algorithm complexity and it can be calculated by using complexity information. Generally, the complexity of a S/W is estimated by the microprocessor simulator. But, the simulation takes long time why the simulator is a software modeled the hardware and it only provides the information about computational complexity quantitatively. In this paper, we propose a complexity estimation method of analysis of S/W on source code level and produce the complexity metric mathematically. The function-wise complexity metrics give the detailed information about the calculation-concentrated location in function. The performance of the proposed method is compared with the result of the gate-level microprocessor simulator 'SimpleScalar'. The used softwares for performance test are $4{\times}4$ integer transform, intra-prediction and motion estimation in the latest video codec, H.264/AVC. The number of executed instructions are used to estimate quantitatively and it appears about 11.6%, 9.6% and 3.5% of error respectively in contradistinction to the result of SimpleScalar.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.57-63
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• 2014

This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.4
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• pp.64-72
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• 2008

Researchers nowadays are trying to implement u-Healthcare (ubiquitous Healthcare) systems for real-time monitoring and analysis of patients' status through a low-cost and low-power wireless sensor network. u-Healthcare system has an aim to provide reliable and fast medical services for patients regardless of time and space by transmitting to doctors a large quantity of vital signs collected from sensor networks. Existing u-Healthcare systems can merely monitor patients' health status. However, it is not easy to derive physiologically meaningful results by analyzing rapidly vital signs through the existing u-Healthcare systems. We introduce a Grid computing technology for deriving the results by analyzing rapidly the vital signs collected from the sensor network. Since both sensor network and Grid computing use different protocols, a gateway is needed. In addition, we also need to construct a gateway which includes the functions such as an efficient management and control of the sensor network, real-time monitoring of the vital signs and communication services related to the Grid network for providing u-Healthcare services effectively. In this paper, to build an advanced u-Healthcare system by using these two technologies most efficiently, we design and present the results to implement a SensorGrid gateway which connects transparently the sensor network and the grid network.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.20-35
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• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.45-54
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• 2006

This paper proposed color matching technique, including display characterization, chromatic adaptation model, and gamut mapping and extension, to generate consistent colors for the same input signal in each display device. It is necessary to characterize the relationship between input and output colors for display device, to apply chromatic adaptation model considering the difference of reference white, and to compensate for the gamut which display devices can represent for reproducing consistent colors on DTV display devices. In this paper, 9 channel-independent GOG model, which is improved from conventional 3 channel GOG(gain, offset gamma) model, is used to consider channel interaction and enhance the modeling accuracy. Then, the input images have to be adjusted to compensate for the limited gamut of each display device. We proposed the gamut mapping and extension method, preserving lightness and hue of an original image and enhancing the saturation of an original image in xy chromaticity diagram. Since the hmm visual system is more sensitive to lightness and hue, these values are maintained as the values of input signal, and the enhancement of saturation is changed to the ratio of input and output gamut. Also the xy chromaticity diagram is effective to reduce the complexity of establishing gamut boundary and the process of reproducing moving-pictures in DTV display devices. As a result, reproducing accurate colors can be implemented when the proposed method is applied to LCD and PDP display devices

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.58-66
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• 2006

In this paper, we apply DCM(Dilation of Color and Motion information) mask and Active Contour Models(Snakes) to extract facial outline in moving pictures with complex background. First, we propose DCM mask which is made by applying morphology dilation and AND operation to combine facial color and motion information, and use this mask to detect facial region without complex background and to remove noise in image energy. Also, initial curves are automatically set according to rotational degree estimated with geometric ratio of facial elements to overcome the demerit of Active Contour Models which is sensitive to initial curves. And edge intensity and brightness are both used as image energy of snakes to extract contour at parts with weak edges. For experiments, we acquired total 480 frames with various head-poses of sixteen persons with both eyes shown by taking pictures in inner space and also by capturing broadcasting images. As a result, it showed that more elaborate facial contour is extracted at average processing time of 0.28 seconds when using interpolated initial curves according to facial rotation degree and using combined image energy of edge intensity and brightness.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.129-138
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• 2014

This paper proposes a fast intra prediction method to reduce encoding time for the HEVC(high-efficiency video coding) encoder. The proposed fast Intra prediction method uses quadtree structure and SATD(Sum of Absolute Transformed Differences). In HEVC, a $8{\times}8$ SATD value using $8{\times}8$ hadamard transform is used to calculate a SATD value for $8{\times}8$ or larger blocks. The proposed method calculates the best SATD value by using each $8{\times}8$ SATD result in $16{\times}16$ or larger blocks. After that, the proposed method removes a candidate mode for RDO(Rate-Distortion Optimization) based on comparing SATD of the candidate mode and the best SATD. By removing candidate modes, the proposed method reduces the operation of RDO and reduces total encoding time. In $8{\times}8$ block, the proposed method uses additional $4{\times}4$ SATD to calculat the best SATD. The experimental results show that the proposed method achieved 5.08% reduction in encoding time compared to the HEVC test model 12.1 encoder with almost no loss in compression performance.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.742-755
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• 2012

In this paper, we propose a parallel deblocking algorithm to resolve workload imbalance when the deblocking filter of high efficiency video coding (HEVC) decoder is parallelized. In HEVC, the deblocking filter which is one of the in-loop filters conducts two-step filtering on vertical edges first and horizontal edges later. The deblocking filtering can be conducted with high-speed through data-level parallelism because there is no dependency between adjacent edges for deblocking filtering processes. However, workloads would be imbalanced among regions even though the same amount of data for each region is allocated, which causes performance loss of decoder parallelization. In this paper, we solve the problem for workload imbalance by predicting the complexity of deblocking filtering with coding unit (CU) depth information at a coding tree block (CTB) and by allocating the same amount of workload to each core. Experimental results show that the proposed method achieves average time saving (ATS) by 64.3%, compared to single core-based deblocking filtering and also achieves ATS by 6.7% on average and 13.5% on maximum, compared to the conventional uniform data-level parallelism.