• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.419-422
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• 2024

최근 인공지능 기술의 발전과 함께 기계학습과 빅데이터를 융합한 서비스가 증가하게 되었고, 무분별한 데이터 수집과 학습으로 인한 개인정보 유출 위험도가 커졌다. 따라서 프라이버시를 보호하면서 기계학습을 수행할 수 있는 기술이 중요해졌다. 동형암호 기술은 정보 주체자의 개인정보 기밀성을 유지하면서 기계학습을 할 수 있는 방법 중 하나이다. 그러나 평문 크기에 비례하여 암호문 크기와 연산 결과의 노이즈가 커지는 동형암호의 특징으로 인해 기계학습 모델의 예측 정확도가 감소하고 학습 시간이 오래 소요되는 문제가 발생한다. 본 논문에서는 부분 동형암호화된 데이터셋으로 로지스틱 회귀 모델을 학습할 수 있는 기법을 제안한다. 실험 결과에 따르면 제안하는 기법이 종래 기법보다 예측 정확도를 59.4% 향상시킬 수 있었고, 학습 소요 시간을 63.6% 개선할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.948-956
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• 2010

Griffiths and Jim has proposed a beamforming structure called GSC algorithm, in which antenna elements are grouped into main-channel and sub-channel, and sidelobe is reduced by applying adaptive LMS algorithm. This paper proposes WLMS-GSC algorithm where the Haar and Daubechies wavelet filters are used to process array antenna output, instead of using subtractor filter. We analyze characteristics of the proposed WLMS-GSC algorithm. The WLMS-GSC has characteristic of reducing the computational requirement one-half compared to the LMS-GSC algorithm. In addition, we obtain MSE characteristics and adaptive beampattern of WLMS-GSC algorithm, and compared with the performance of LMS-GSC algorithm. The simulation results show that the WLMS-GSC algorithm proposed in this paper gives better or almost the same performance, compared to the LMS-GSC algorithm. In addition, the newly proposed structure has advantage of low computational requirements.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.454-460
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• 2003

In this paper, we present a novel method of parallelization of the modular multiplication algorithm to improve time and space complexity on RNS (Residue Number System). The parallel algorithm executes modular reduction using new table lookup based reduction method. MRS (Mixed Radix number System) is used because algebraic comparison is difficult in RNS which has a non-weighted number representation. Conversion from residue number system to certain MRS is relatively fast in residue computer. Therefore magnitude comparison is easily Performed on MRS. By the analysis of the algorithm, it is known that it requires only 1/2 table size than previous approach. And it requires 0(ι) arithmetic operations using 2ㅣ processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1172-1179
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• 2022

This paper describes a design of point scalar multiplier for public-key cryptography based on binary Edwards curves (BEdC). For efficient implementation of point addition (PA) and point doubling (PD) on BEdC, projective coordinate was adopted for finite field arithmetic, and computational performance was improved because only one inversion was involved in point scalar multiplication (PSM). By applying optimizations to hardware design, the storage and arithmetic steps for finite field arithmetic in PA and PD were reduced by approximately 40%. We designed two types of point scalar multipliers for BEdC, Type-I uses one 257-b×257-b binary multiplier and Type-II uses eight 32-b×32-b binary multipliers. Type-II design uses 65% less LUTs compared to Type-I, but it was evaluated that it took about 3.5 times the PSM computation time when operating with 240 MHz. Therefore, the BEdC crypto core of Type-I is suitable for applications requiring high-performance, and Type-II structure is suitable for applications with limited resources.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.

• The Journal of the Acoustical Society of Korea
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• v.20 no.3
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• pp.34-41
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• 2001

In an IMBE (Improved Multi-band Excitation) speech coder, initial pitch estimation occupies most of the total computing time for the coder due to complex cost function and exhaustive search over candidate pitches. Future frames in initial pitch estimation cause inevitable time delay. Therefore, it is difficult to implement a real-time coder. Furthermore, unvoiced frames use the unnecessary pitch estimation as in the voiced frames. In this paper, each frame is determined voiced or unvoiced by Dyadic Wavelet Transform (DyWT) and, then, initial pitch estimation is performed only for voiced frame. Therefore different pitch estimation algorithms are employed between voiced and unvoiced frames incurring reduced time delay at transmitter and receiver. Simulation result show that the relative complexity of initial pitch estimation is reduced by 23％, and the processing time decreases down to 1/10 ∼ 1/1l of the IMBE coder while speech quality is almost maintained.

• Journal of Advanced Navigation Technology
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• v.4 no.1
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• pp.67-77
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• 2000

This paper proposes a reduction scheme for codebook search time in the adaptive codebook using wavelet transformed coefficients. In a CELP coder, pitch estimation with a combined open loop and closed loop search in adaptive codebook needs a lengthy search. More precisely, the pitch search using autocorrelation function over all possible ranges has been shown inefficient compared to the consuming time. In this paper, we propose a new adaptive codebook search algorithm which ensures the same position for the pitch with maximum wavelet coefficient over various scaling factors in Dyadic wavelet transform. A new adaptive codebook search algorithm reduces 25% conventional search time with almost the same quality of speech.

• Korean Journal of Remote Sensing
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• v.34 no.6_2
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• pp.1215-1227
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• 2018

Sea ice motion is an important factor for assessing change of sea ice because the motion affects to not only regional distribution of sea ice but also new ice growth and thickness of ice. This study presents an application of multi-temporal high-resolution optical satellites images obtained from Korea Multi-Purpose Satellite-2 (KOMPSAT-2) and Korea Multi-Purpose Satellite-3 (KOMPSAT-3) to measure sea ice motion using SIFT (Scale-Invariant Feature Transform), SURF (Speeded Up Robust Features) and ORB (Oriented FAST and Rotated BRIEF) feature tracking techniques. In order to use satellite images from two different sensors, spatial and radiometric resolution were adjusted during pre-processing steps, and then the feature tracking techniques were applied to the pre-processed images. The matched features extracted from the SIFT showed even distribution across whole image, however the matched features extracted from the SURF showed condensed distribution of features around boundary between ice and ocean, and this regionally biased distribution became more prominent in the matched features extracted from the ORB. The processing time of the feature tracking was decreased in order of SIFT, SURF and ORB techniques. Although number of the matched features from the ORB was decreased as 59.8% compared with the result from the SIFT, the processing time was decreased as 8.7% compared with the result from the SIFT, therefore the ORB technique is more suitable for fast measurement of sea ice motion.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.29-40
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• 2008

The efficient hardware design of finite field multiplication is an very important research topic for and efficient $f(x)=x^n+x^k+1$ implementation of cryptosystem based on arithmetic in finite field GF($2^n$). We used special generating trinomial to construct a bit-parallel multiplier over finite field with low space complexity. To reduce processing time, The hardware architecture of proposed multiplier is similar with existing Mastrovito multiplier. The complexity of proposed multiplier is depend on the degree of intermediate term $x^k$ and the space complexity of the new multiplier is $2k^2-2k+1$ lower than existing multiplier's. The time complexity of the proposed multiplier is equal to that of existing multiplier or increased to $1T_X(10%{\sim}12.5%$) but space complexity is reduced to maximum 25%.