• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.1176-1177
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• 2011

본 논문에서는 모바일 청진기로 언제 어디서나 고령자의 건강상태를 진단할 수 있는 건강 및 질환관리 시스템을 제안하며, 이를 통해 현재의 전문의 중심의 청진기 진료에서 누구나 쉽게 자가진단이 가능한 u-헬스케어 서비스를 제공하고자 한다. 본 시스템은 디지털 청진기와 스마트폰 모바일 어플리케이션을 연동하여 청진신호를 파형으로 시각화하여 사용자가 편리하게 건강상태를 자가진단 할 수 있도록 서비스하며 또한, 웹 서버를 통해 전문의의 상세진단을 받을 수 있다.

• The Journal of the Acoustical Society of Korea
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• v.33 no.4
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• pp.262-267
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• 2014

Recently, long pulses are transmitted for target detection in active sonar application. Matched filtering implemented by simple convolution algorithm, requires massive computational power for long replica. The computational loads are reduced significantly by implementing the convolution in the frequency domain with overlap add method, but the performance degrades for specified input/output system delay which constrains the size of FFT function. For performance improvement, the replica could be partitioned into uniform blocks (FDL) by re-using IFFT operations, or variable blocks of increasing length (MC) by using the largest possible blocks to calculate the convolution. In this paper, by combining the strong points of the two methods, we propose a new filter partition structure that allows for further optimization of the previous two methods.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.298-306
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• 2011

In this paper, the RUNCODE encoder hardware IP was designed and implemented for symbol ID code length encoding, which is one of major modules of JBIG2 encoder for FAX. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the hardware generation and synthesis of VHDL code. The synthesized hardware was downloaded to Virtex-4 FX60 FPGA on ML410 development board. The synthesized hardware utilizes 13% of total slice of FPGA. Using Active-HDL tool, the hardware was verified showing normal operation. Compared with the software operating using Microblaze cpu on ML410 board, the synthesized hardware was better in operation time. The improvement ratio of operation time between the synthesized hardware and software showed about 40 times faster than software only operation. The synthesized H/W and S/W module cooperated to succeed in compressing the CCITT standard document.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.182-192
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• 2010

This paper proposes the hardware IP design of JBIG2 encoder. In order to facilitate the next generation FAX after the standardization of JBIG2, major modules of JBIG2 encoder are designed and implemented, such as symbol extraction module, Huffman coder, MMR coder, and MQ coder. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the synthesis of VHDL code. To minimize the memory usage, 128 lines of input image are processed succesively instead of total image. The synthesized IPs are downloaded to Virtex-4 FX60 FPGA on ML410 development board. The four synthesized IPs utilize 36.7% of total slice of FPGA. Using Active-HDL tool, the generated IPs were verified showing normal operation. Compared with the software operation using microblaze cpu on ML410 board, the synthesized IPs are better in operation time. The improvement ratio of operation time between the synthesized IP and software is 17 times in case of symbol extraction IP, and 10 times in Huffman coder IP. MMR coder IP shows 6 times faster and MQ coder IP shows 2.2 times faster than software only operation. The synthesized H/W IP and S/W module cooperated to succeed in compressing the CCITT standard document.