• Proceedings of the KAIS Fall Conference
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• 2011.12b
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• pp.434-437
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• 2011

본 논문에서는 H.264/AVC 복호기의 성능을 향상시키기 위해 병렬 역양자화 구조와 역변환 구조를 제안한다. 제안하는 역양자화 구조는 공통 연산기를 사용하여 계산 복잡도를 감소시키고, 4개의 공통연산기를 사용하여 역양자화 수행 사이클 수를 1 사이클로 감소시킨다. 제안하는 역변환 구조는 4개의 변환 연산기를 사용하여 역변환 연산을 수행하는데 2 사이클이 소요된다. 또한 제안하는 구조는 역양자화 연산과 수평 역변환 연산을 동시에 수행하는 병렬 구조를 채택하여 역양자화 및 역변환 수행 사이클 수를 2 사이클로 감소시킨다. 제안하는 구조를 Magnachip 0.18um CMOS 공정 라이브러리를 이용하여 합성한 결과 1.5MHz의 동작 주파수에서 게이트 수는 14,173이고, 표준 참조 소프트웨어 JM 9.4에서 추출한 데이터를 이용하여 성능을 측정한 결과 제안하는 구조의 수행 사이클 수가 기존 구조 대비 38.74% 향상되었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2253-2260
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• 2012

In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.444-447
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• 2011

In this paper, parallel IT(inverse transform) architecture and IQ(inverse quantization) architecture with common operation unit for the H.264/AVC decoder are proposed. By using common operation unit, the area cost and computational complexity of IQ are reduced. In order to take four execution cycles to perform IT, the proposed IT architecture has parallel architecture with one horizontal DCT unit and four vertical DCT units. Furthermore, the execution cycles of the proposed architecture is reduced to five cycles by applying two state pipeline architecture. The proposed architecture is implemented to a single chip by using Magnachip 0.18um CMOS technology. The gate count of the proposed architecture is 14.3k at clock frequency of 13MHz and the area of proposed IQ is reduced 39.6% compared with the previous one. The experimental result shows that execution cycle the proposed architecture is about 49.09% higher than that of the previous one.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.7
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• pp.296-303
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• 2007

Color quantization replaces the color of each pixel with the closest representative color, and thus it makes the resulting image partitioned into uniformly-colored regions. As a consequence, continuous, detailed variations of color over the corresponding regions in the original image are lost through color quantization. In this paper. we present a novel blind scheme for restoring such variations from a color-quantized input image without it priori knowledge of the quantization method. Our scheme identifies which pairs of uniformly-colored regions in the input image should have continuous variations of color in the resulting image. Then, such regions are seamlessly stitched through optimization while preserving the closest representative colors. The user can optionally indicate which regions should be separated or stitched by scribbling constraint brushes across the regions. We demonstrate the effectiveness of our approach through diverse examples, such as photographs, cartoons, and artistic illustrations.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.446-451
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• 2010

This paper addressed an another scheme of distortion estimation method based on simplified inverse quantization in H.264/AVC. The distortion is calculated by the difference of coefficient between quantized transform coefficients and that of inverse. In general, these process included such transforms as discrete cosine transform(DCT), quantization, inverse quantization(IQ), and Inverse DCT(IDCT). In proposed approach, IQ as well as IDCT process are skipped because of replacing a couple of approximated formulas. Some simulation have been conducted and it showed that the PSNR was almost the same, and reduced the rate-distortion optimization(RDO) mode decision time of 8~15% in comparison with conventional method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.857-864
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• 2004

Many image compression standards such as JPEG, MPEG or H.263 are based on the discrete cosine transform (DCT) and quantization method. Quantization error. is the major source of image quality degradation. The current dequantization method assumes the uniform distribution of the DCT coefficients. Therefore the dequantization value is the center of each quantization interval. However DCT coefficients are regarded to follow Laplacian probability density function (pdf). The center value of each interval is not optimal in reducing squared error. We use mean of the quantization interval assuming Laplacian pdf, and show the effect of correction on image quality. Also, we compare existing quantization error to corrected quantization error in closed form. The effect of PSNR improvements due to the compensation to the real image is in the range of 0.2 ∼0.4 ㏈. The maximum correction value is 1.66 ㏈.

• Journal of Broadcast Engineering
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• v.11 no.4 s.33
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• pp.386-395
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• 2006

Multi-view video coding technology demands the very high efficient coding technologies, because it has to encode a number of video sequences which are achieved from a number of video cameras. For this purpose, multi-view video coding introduces the inter-view prediction scheme between different views, but it shows a limitation of coding performance enhancement by adopting only new prediction method. Accordingly, we are going to achieve the more coding performance by enhancing dequantizer perfermance. Multi-view video coding is implemented basically based on H.264/AVC and uses the same quantization/de-quantization method as H.264/AVC does. The conventional quantizer and dequantizer is designed with the assumption that input residual signal follows the Laplacian PDF. However, it doesn't follow the fixed PDF type always. This mismatch between assumption and real data causes degradation of coding performance. To solve this problem, we propose the efficient de-quantization method based on quantized coefficients distribution at decoder without extra information. The extensive simulation results show that the proposed algorithm produces maximum $1.5\;dB{\sim}0.6\;dB$ at high bitrate compared with that of conventional method.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.06a
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• pp.489-493
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• 1990

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.173-176
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• 2000

본 논문은 VHDL을 이용하여 1997년 국제 표준안으로 제정된 MPEG-2 AAC 복호화기의 각 모듈을 구현하였다. AAC 복호화기는 허프만 복호화, 역양자화, 고해상도 필터뱅크 등의 도구들이 필수적으로 사용된다. AAC 복호화기의 실시간 구현을 위해 각 도구들의 알고리즘을 분석하고, 하드웨어 개발에 알맞게 최적화하여 고속화와 적은 메모리를 사용하여 효율적으로 구현하였다.