• Title/Summary/Keyword: 압축 칩

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Study on Vibrated Cutting Blade with Hinge Mechanism (힌지구조 진동절단장치에 관한 연구)

  • Kang, Dong-Bae;Ahn, Joong-Hwan;Son, Seong-Min
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.2
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    • pp.443-448
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    • 2010
  • Rapid advance in information technology requires high performance devices with compact size. Integrated multi-layer electronic element with different functions enables those compact devices to possess various performances and powerful capabilities. In mass production, the multi-layer electronic element is manufactured as a bulk type with a large number of parts for productivity. However, this may cause the electronic part to be damaged in the cutting process of the bulk elements to separate into each part. Therefore the cutting performance of multi-layer element bulk is playing an important role in the view of production efficiency. This study focuses on the cutting characteristics of multi-layer electronic elements. In order to increase the efficiency, the vibration cutting method was applied to the blade cutting machine. Flexure hinge structure, which is an physical amplifier of increasing displacement, was attached to the vibration cutting device for machining efficiency. The behaviors of flexure hinge were modeled with Lagrange equation and simulated with finite element method (FEM). Performance of hinge structure was verified by experimental modal analysis (EMA) for hinge structure to be tuned to the specific mode of vibrations. Cutting experiments of multi-layer elements were conducted with the proposed vibrating cutting module, and the characteristics was analyzed.

Hardware Design for JBIG2 Huffman Coder (JBIG2 허프만 부호화기의 하드웨어 설계)

  • Park, Kyung-Jun;Ko, Hyung-Hwa
    • Journal of Korea Multimedia Society
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    • v.12 no.2
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    • pp.200-208
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    • 2009
  • JBIG2, as the next generation standard for binary image compression, must be designed in hardware modules for the JBIG2 FAX to be implemented in an embedded equipment. This paper proposes a hardware module of the high-speed Huffman coder for JBIG2. The Huffman coder of JBIG2 uses selectively 15 Huffman tables. As the Huffman coder is designed to use minimal data and have an efficient memory usage, high speed processing is possible. The designed Huffman coder is ported to Virtex-4 FPGA and co-operating with a software modules on the embedded development board using Microblaze core. The designed IP was successfully verified using the simulation function test and hardware-software co-operating test. Experimental results shows the processing time is 10 times faster than that of software only on embedded system, because of hardware design using an efficient memory usage.

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The Customer Premise Platform for Processing Multimedia Data on the ATM network (ATM망의 멀티미디어 데이터 처리를 위한 가입자단 플랫폼)

  • Kim Yunhong;Son Yoonsik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.2 s.332
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    • pp.89-96
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    • 2005
  • In this paper, we propose a customer premise platform for processing multimedia data service on the ATM network. The proposed platform has a specific AAL2 processor that includes AAL2 protocol and scheduler algorithm so as to off-load large potion of burden from host processor and make it easy to process multimedia data from the ATM network in real time compared with conventional platform in which AAL/ATM tasks are processed by software. The ATS scheduler that is implemented based on 2-level time slot ring provides a simple and efficient method for scheduling data of VBR-rt, UBR and CBR traffics. TMS320C5402 DSP is used to process voice-related tasks such as voice compression and voice packet manupulation and AAL2 processor is implemented on $0.35\;{\mu}m$ process line. We implemented the customer premise equipment for VoDSL service and tested the proposed platform on a test bed network. The experimental results show that the proposed equipment has the call success rate of $97\%$ at least and provides voice service of toll-qualify.

An ASIC Implementation of Digital NTSC/PAL Video Encoder (디지탈 NTSC/PAL 비디오 부호화기의 ASIC 구현)

  • Oh, Seung-Ho;Lee, Moon-Key
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.6
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    • pp.109-118
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    • 1998
  • This paper presents an ASIC implementation of video encoder which converts either digital RGB or YCbCr to S-video(Y/C) and composite video signal. The video timing signal of this encoder includes horizontal sync., vertical sync. signal and blanking, and this encoder supports field identification signal which is convenient for video editing. The encoder has been designed in the 4 stages pipeline structure to assure the stable operation of each submodule. The proposed encoder requires only 20K gates ,which is a 40% reduction in hardware compared with [13]. The designed encoder was fabricated in $0.65{\mu}m$ SOG triple metal CMOS technology. Chip size is $3.7478mm {\times} 4.4678mm$ including PAD, gate counts is 19,468 and dissipated power is 0.9W.

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A VLSI Implementation of Real-time 8$\times$8 2-D DCT Processor for the Subprimary Rate Video Codec (저 전송률 비디오 코덱용 실시간 8$\times$8 이차원 DCT 처리기의 VLSI 구현)

  • 권용무;김형곤
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.15 no.1
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    • pp.58-70
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    • 1990
  • This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

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Hardware Design of Efficient SAO for High Performance In-loop filters (고성능 루프내 필터를 위한 효율적인 SAO 하드웨어 설계)

  • Park, Seungyong;Ryoo, Kwangki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.10a
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    • pp.543-545
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    • 2017
  • This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

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Adaptive Block Watermarking Based on JPEG2000 DWT (JPEG2000 DWT에 기반한 적응형 블록 워터마킹 구현)

  • Lim, Se-Yoon;Choi, Jun-Rim
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.101-108
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    • 2007
  • In this paper, we propose and verify an adaptive block watermarking algorithm based on JPEG2000 DWT, which determines watermarking for the original image by two scaling factors in order to overcome image degradation and blocking problem at the edge. Adaptive block watermarking algorithm uses 2 scaling factors, one is calculated by the ratio of present block average to the next block average, and the other is calculated by the ratio of total LL subband average to each block average. Signals of adaptive block watermark are obtained from an original image by itself and the strength of watermark is automatically controlled by image characters. Instead of conventional methods using identical intensity of a watermark, the proposed method uses adaptive watermark with different intensity controlled by each block. Thus, an adaptive block watermark improves the visuality of images by 4$\sim$14dB and it is robust against attacks such as filtering, JPEG2000 compression, resizing and cropping. Also we implemented the algorithm in ASIC using Hynix 0.25${\mu}m$ CMOS technology to integrate it in JPEG2000 codec chip.

Thermal and Flow Analysis of a Driving Controller for Active Destruction Protections (능동 파괴 방호 구동제어기의 열 유동 해석)

  • Ryu, Bong-Jo;Oh, Bu-Jin;Kim, Youngshik
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.2
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    • pp.235-242
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    • 2017
  • A driving controller for active destruction protections can be applied to machinery, aerospace and military fields. In particular, this controller can be used to track and attack enemy flying objects through the active control. It is important to ensure reliability of the driving controller since its operation should be kept with precision to the target point. The temperature of the environment where the driving controller is used is about -32 C ~ 50 C (241~323 ). Heat generated in the driving controller should be maintained below a certain threshold (85 C (358 )) to ensure reliability; therefore, the study and analysis of the heat flow characteristics in the driving controller are required. In this research, commercial software Solid-Works Flow Simulation was used for the numerical simulation assuming a low Reynolds number turbulence model and an incompressible viscous flow. The goal of this paper is to design the driving controller safely by analyzing the characteristics of the heat flow inside of the controller composed of chips or boards. Our analysis shows temperature distributions for boards and chips below a certain threshold.

Dual BTC Image Coding technique for Full HD Display Driver (Full HD 디스플레이 드라이버를 위한 Dual BTC 영상부호화 기법)

  • Kim, Jin-Hyung;Ko, Yun-Ho
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.49 no.4
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    • pp.1-9
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    • 2012
  • LCD(Liquid Crystal Display) commonly used as an output device has a drawback of slow response time compared with CRT display. This drawback causes motion blur especially when an abrupt intensity change occurs in an image sequence as time goes on. To overcome the problem of slow response time overdriving technique has been used in TCON of LCD. In this technique, the previous frame data has to be compressed and stored in an external memory. Considering both chip size of TCON and computational complexity, AM-BTC has been applied to the 8bit HD display driver. However, the conventional method is not suitable for 10 bit Full HD because 10 bit Full HD data is much larger than that of 8 bit HD data. Being applied to 10 bit Full HD display driver, the conventional method increase cost by enlarging the external memory size of TCON or deteriorates image quality. In this paper, we propose dual BTC image coding technique for Full HD display driver that is an adaptive coding scheme according to morphological information of each sample block. Through experiments, it is verified that the proposed Dual BTC method performs better than the conventional method not only quantitatively but also qualitatively.

Developement of Small 360° Oral Scanner Embedded Board for Image Processing (소형 360° 구강 스캐너 영상처리용 임베디드 보드 개발)

  • Ko, Tae-Young;Lee, Sun-Gu;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1214-1217
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    • 2018
  • In this paper, we propose the development of a Small $360^{\circ}$ Oral Scanner embedded board. The proposed small $360^{\circ}$ oral scanner embedded board consists of image level and transfer method changing part FPGA part, memory part and FIFO to USB transfer part. The image level and transmission mode change unit divides the MIPI format oral image received through the small $360^{\circ}$ oral cavity image sensor and the image sensor into low power signal mode and high speed signal mode and distributes them to the port and transfers the level shift to the FPGA unit. The FPGA unit performs functions such as $360^{\circ}$ image distortion correction, image correction, image processing, and image compression. In the FIFO to USB transfer section, the RAW data transferred through the FIFO in the FPGA is transferred to the PC using USB 3.0, USB 3.1, etc. using the transceiver chip. In order to evaluate the efficiency of the proposed small $360^{\circ}$ oral scanner embedded board, it has been tested by an authorized testing institute. As a result, the frame rate per second is over 60 fps and the data transfer rate is 4.99 Gb/second