• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.143-150
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• 2013

Solid-state disks (SSDs) have been widely used by high-performance personal computers or servers due to its good characteristics and performance. The NAND flash-based SSDs, which take large portion of the whole NAND flash market, are the major type of SSDs. They usually integrate a cache buffer which is built from DRAM and uses the write-back policy for better performance. Unfortunately, the policy makes existing scheduling methods less effective at the I/F level of SSDs Therefore, in this paper, we propose a scheduling method for the I/F with consideration of the cache buffer. The proposed method considers the hit/miss status of cache buffer and gives higher priority to the read requests. As a result, the requests whose data is hit on the cache buffer can be handled in advance and the read requests which have larger effects on the whole system performance than write requests experience shorter latency. The experimental results show that the proposed scheduling method improves read latency by 26%.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.634-641
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• 2006

Flash memory has many advantages like non-volatility and fast I/O speed, but it has also disadvantages such as not-in-place-update data and asymmetric read/write/erase speed. For the performance of flash memory storage, it is essential for the buffer replacement algorithms to reduce the number of write operations that also affects the number of erase operations. A new buffer replacement algorithm is proposed in this paper, that delays the writes of not-cold-dirty pages in the buffer cache of flash storage. We show that this algorithm effectively decreases the number of write operations and erase operations without much degradation of hit ratio. As a result overall performance of flash I/O speed is improved.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• Journal of Korea Multimedia Society
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• v.8 no.4
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• pp.439-449
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• 2005

Distributed main memory database management systems (DMM-DBMSs) store the database in main memories of the participating sites. They provide high performance through fast access to the local databases and high speed communication among the sites. Recently, a lot of research results on DMM- DBMSs has been reported. However, to the best of our knowledge, there is no known research result on the performance of the catalog management schemes for DMM-DBMSs. In this work, we evaluated the performance of the partitioned catalog management schemes through experimental analysis. First, we classified the partitioned catalog management schemes into three categories : Partitioned Catalogs Without Caching (PCWC), Partitioned Catalogs With Incremental Caching (PCWIC), and Partitioned Catalogs With Full Caching (PCWFC). Experiments were conducted by varying the number of sites, the number of terminals per site, buffer size, write query ratio, and local query ratio. Experiments show that PCWFC outperforms the other two schemes in all cases. It also means that the performance of PCWIC gradually increases as time goes by. It should be noted that PCWFC does not guarantee high performance for disk-based distributed DBMSs in cases when the workload of individual site is high, catalog write ratio is high, or remote data objects are accessed very frequently. Main reason that PCWFC outperforms for DMM-DBMSs is that query compilation and remote catalog access can be done in a very high speed, even when the catalogs of the remote data objects are frequently updated.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.07a
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• pp.235-236
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• 2014

플래시 메모리 기술이 발전함에 따라 낸드 플래시 기반의 SSD가 상용화 되면서 I/O시간을 줄이기 위한 연구들이 진행되고 있다. 이에 본 논문에서는 기존의 메인 메모리와 저장장치 사이에 확장 버퍼 캐시로써 SSD를 사용하고 메인 메모리에서 방출 된 페이지들을 구분하여 같은 성향의 페이지들을 블록화 하는 모델을 제안한다. 이러한 모델을 통하여 블록 단위로 사용되는 SSD를 효율적으로 이용하여 읽기 및 쓰기 성능을 높이고 I/O에 해당하는 시간들을 줄임으로써 전체적인 성능 향상을 증명하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.298-303
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• 2007

비휘발성 메모리의 하나인 플래시 메모리는 저전력 및 저비용 등의 장점으로 인해 임베디드 시스템에 필수적인 요소로 사용되고 있다. 이러한 장점에 반해, DRAM과 같은 휘발성 반도체 메모리와 비교하여 데이터 쓰기는 느리고, 데이터 업데이트를 위한 블록 소거 (erase) 동작의 오버헤드라는 단점이 있다. 특히 블록 소거 동작은 횟수가 제한되어 있으며, 이는 플래시 메모리의 수명을 결정하는데 중요한 요소이다. 본 논문에서는 플래시 메모리 기반 파일시스템에서 DRAM과 같은 동적 메모리를 사용하여 블록 소거의 횟수를 줄이고 입출력 속도를 향상시키는 기법을 제안한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.77-78
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• 2009

In this paper, we study a pattern-aware write cache policy using a NAND flash memory in disk-based mobile storage systems. Our work is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk. Experimental results show that our policy improves the overall I/O performance by reducing the overhead significantly from a non-volatile cache over a traditional one.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.31 no.5
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• pp.365-373
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• 2013

Tile caching technology is a commonly used method that optimizes the delivery of map imagery across the internet in modern WebGIS systems. However the poor performance of the map tile cache update is one of the major causes that hamper the wider use of this technique for datasets with frequent updates. In this paper, we introduce a new algorithm, namely, Partial Area Cache Update (PACU) that significantly minimizes redundant update of map tiles where the update frequency of source map data is very large. The performance of our algorithm is verified with the cadastral map data of Pyeongtaek of Gyeonggi Province, where approximately 3,100 changes occur in a day among the 331,594 parcels. The experiment results show that the performance of the PACU algorithm is 6.6 times faster than the ESRI ArcGIS SERVER$^{(r)}$. This algorithm significantly contributes in solving the frequent update problem and enable Web Map Tile Services for data that requires frequent update.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.15-20
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• 2016

Write amplification is a critical factor that limits the stable performance of flash-based storage systems. To reduce write amplification, this paper presents a new technique that cooperatively manages data in flash storage and nonvolatile memory (NVM). Our scheme basically considers NVM as the cache of flash storage, but allows the original data in flash storage to be invalidated if there is a cached copy in NVM, which can temporarily serve as the original data. This scheme eliminates the copy-out operation for a substantial number of cached data, thereby enhancing garbage collection efficiency. Experimental results show that the proposed scheme reduces the copy-out overhead of garbage collection by 51.4% and decreases the standard deviation of response time by 35.4% on average.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.1-10
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• 2015

NAND flash systems require deletion operation and do not support in-place update, so the storage systems should use Flash Translation Layer (FTL). However, there are a lot of memory consumptions using mapping table in the FTL, so recently, many studies have been proposed to resolve mapping table overhead. These studies try to solve update propagation problem in the nand flash system which does not use mapping table. In this paper, we present a novel index structure, called CL-Tree(Cache List Tree), to solve the update propagation problem. The proposed index structure reduces write operations which occur for an update propagation, and it has a good performance for search operation because it uses multi-list structure. In experimental evaluation, we show that our scheme yields about 173% and 179% improvement in insertion speed and search speed, respectively, compared to traditional B+tree and other works.