• Korean Journal of Materials Research
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• v.4 no.7
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• pp.759-766
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• 1994

Our investigation aimed to reduce the leakage current of $Ta_2O_5$ thin film capacitor by layering SnOz thin film layer under Ta thin film, thereby supplying extra oxygen ions from the $SnO_{2}$ underlayer to enhance the stoichiometry of $Ta_2O_5$ during the oxidation of Ta thin film. Tantalum was evaporated by e-beam or sputtered on p-Si wafers with various deposition temperatures and was oxidized by dry--oxygen at the temperatures between $500^{\circ}C$ and $900^{\circ}C$. Aluminum top and bottom electrodes were formed to make Al/$Ta_2O_5$/p-Si/Al or $Al/Ta_2O_5/SnO_2$p-Si/AI MIS type capacitors. LCR meter and pico-ammeter were used to measure the dielectric constants and leakage currents of the prepared thm film capacitors. XRD, AES and ESCA were employed to confirm the crystallization of the thin f~lm and the compositions of the films. Dielectric constant of $Ta_2O_5$ thin film capacitor with $SnO_{2}$ underlayer was found to be about 200, which is about 10 times higher than that of $Ta_2O_5$ thin film capacitor without $SnO_{2}$ underlayer. In addition, higher oxidation temperatures increased the dielectric constants and reduced the leakage current. Higher deposition temperature generally gave lower leakage current. $Ta_2O_5/SnO_2$ capacitor deposited at $200^{\circ}C$ and oxidized at $800^{\circ}C$ showed significantly lower leakage current, $10^{-7}A/\textrm{cm}^2$ at $4 \times 10^{5}$V/cm, compared to the one without $SnO_{2}$ underlayer. XRD showed that $Ta_2O_5$ thin film was crystallized above $700^{\circ}C$. AES and ESCA showed that initially the $SnO_{2}$, underlayer supplied oxygen ions to oxidize the Ta layer, however, Sn also diffused into the Ta thin film layer to form a new $Ta_xSn_YO_Z$ , ternary oxide layer after all.

• Journal of Navigation and Port Research
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• v.46 no.3
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• pp.179-190
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• 2022

In this study, we investigated the characteristic impedance and bandwidth of CPW3DCS (coplanar waveguide employing periodic 3D coupling structures), and examined its potential for the development of a marine radio communication FISoC (fully-integrated system on chip) semiconductor device. To extract bandwidth and characteristic impedance of the CPW3DC, we induced a measurement-based equation reflecting measured insertion loss, and compared the measured results of the propagation constant β and characteristic impedance with the measured ones. According to the results of the comparison, the calculated results show a good agreement with the measured ones. Concretely, the propagation constant β and characteristic impedance exhibited an maximum error of 3.9% and 6.4%, respectively. According to the results of this study, in a range of LT = 30 ~ 150 ㎛ for the length of periodic structures, the CPW3DC exhibited a passband characteristic of 121 GHz, and a very small dependency of characteristic impedance on frequency. We could realize a low impedance transmission line with a characteristic impedance lower than 20 Ω by using CPW3DCS with a line width of 20 ㎛, which was highly reduced, compared with a 3mm line width of conventional transmission line with the same impedance. The characteristic impedance was easily adjusted by changing LT. The above results indicate that the CPW3DC can be usefully used for the development of a wireless communication FISoC (fully-integrated system on chip) semiconductor device. This is the first report of a study on the bandwidth of the CPW3DC.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• Journal of Sensor Science and Technology
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• v.7 no.3
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• pp.154-162
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• 1998

A planar Bi-Sb multijunction thermal converter with high thermal sensitivity and small ac-dc transfer error has been fabricated by preparing the bifilar thin film Pt-heater and the hot junctions of thin film Bi-Sb thermopile on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$-diaphragm, which functions as a thermal isolation layer, and the cold junctions on the dielectric membrane supported with the Si-substrate, which acts as a heat sink, and its ac-dc transfer characteristics were investigated with the fast reversed dc method. The respective thermal sensitivities of the converter with single bifilar heater were about 10.1 mV/mW and 14.8 mV/mW in the air and vacuum, and those of the converter with dual bifilar heater were about 5.1 mV/mW and 7.6 mV/mW, and about 5.3 mV/mW and 7.8 mV/mW in the air and vacuum for the inputs of inside and outside heaters, indicating that the thermal sensitivities in the vacuum, where there is rarely thermal loss caused by gas, are higher than those in the air. The ac-dc voltage and current transfer difference ranges of the converter with single bifilar heater were about ${\pm}1.80\;ppm$ and ${\pm}0.58\;ppm$, and those of the converter with dual bifilar heater were about ${\pm}0.63\;ppm$ and ${\pm}0.25\;ppm$, and about ${\pm}0.53\;ppm$ and ${\pm}0.27\;ppm$, respectively, for the inputs of inside and outside heaters, in the frequency range below 10 kHz and in the air.