• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.11
• /
• pp.20-25
• /
• 2016

This study addresses a low complexity and lossless frame memory compression algorithm based on block-buffer structure for efficient high resolution video processing. Our study utilizes the block-based MHT (modified Hadamard transform) for spatial decorrelation and AGR (adaptive Golomb-Rice) coding as an entropy encoding stage to achieve lossless image compression with low complexity and efficient hardware implementation. The MHT contains only adders and 1-bit shift operators. As a result of AGR not requiring additional memory space and memory access operations, AGR is effective for low complexity development. Comprehensive experiments and computational complexity analysis demonstrate that the proposed algorithm accomplishes superior compression performance relative to existing methods, and can be applied to hardware devices without image quality degradation as well as negligible modification of the existing codec structure. Moreover, the proposed method does not require the memory access operation, and thus it can reduce costs for hardware implementation and can be useful for processing high resolution video over Full HD.

• Journal of Broadcast Engineering
• /
• v.21 no.4
• /
• pp.562-568
• /
• 2016

In this paper, we focus on recognition of speed-limit signs among a few types of traffic signs because speed-limit sign is closely related to safe driving of drivers. Although histogram of oriented gradient (HOG) and local binary patterns (LBP) are representative features for object recognition, these features have a weakness with respect to rotation, in that it does not consider the rotation of the target object when generating patterns. Therefore, this paper propose the fast rotation-invariant binary patterns (FRIBP) algorithm to generate a binary pattern that is robust against rotation. The proposed FRIBP algorithm deletes an unused layer of the histogram, and eliminates the shift and comparison operations in order to quickly extract the desired feature. The proposed FRIBP algorithm is successfully applied to German Traffic Sign Recognition Benchmark (GTSRB) datasets, and the results show that the recognition capabilities of the proposed method are similar to those of other methods. Moreover, its recognition speed is considerably enhanced than related works as approximately 0.47second for 12,630 test data.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.5
• /
• pp.7-16
• /
• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of Advanced Navigation Technology
• /
• v.24 no.1
• /
• pp.47-52
• /
• 2020

Direction of arrival (DoA) estimation is a scheme of estimating the directions of targets by analyzing signals generated or reflected from the targets and is used in various fields. Artificial neural networks (ANN) is a field of machine learning that mimics the neural network of living organisms. They show good performance in pattern recognition. Although researches has been using ANNs to estimate the DoAs, there are limitationsin dealing with variations of the signal-to-noise ratio (SNR) of the target signals. In this paper, we propose a three-stage ANN algorithm for DoA estimation. The proposed algorithm can minimize the performance reduction by applying the model trained in a single SNR environment to various environments through a 'noise reduction process'. Furthermore, the scheme reduces the difficulty in learning and maintains efficiency in estimation, by employing a process of DoA shift. We compare the performance of the proposed algorithm with Cramer-Rao bound (CRB) and the performances of existing subspace-based algorithms and show that the proposed scheme exhibits better performance than other schemes in some severe environments such as low SNR environments or situations in which targets are located very close to each other.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.243-246
• /
• 2008

This thesis suggests block cipher operating mode using ASR(Arithmetic Shift Register). ASR is ratted arithmetic shift register which is sequence that is not 0 but initial value $A_0$ multiplies not 0 or 1 but free number D on $GF(2^n)$. This thesis proposes ASR mode which changes output multiplying d and Floating ASR mode which has same function but having strengthened stability altering d. If we use ASR's output as a counter, there's advantage that it has higher stability and better speed than CTR. Also, ASR mode and FASR mode have advantage of Random access which is not being functioned on CTR mode, they can be widely used to any part which Random access is needed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.99-102
• /
• 2012

An image scaler is a IP used in a image processing block of display devices to adjust image size. Proposed image scaler adopts line memories instead of a conventional method using a frame memory. This method reduced hardware resources and enhanced data precision by using shift operations that number is multiplied by $2^m$ and divided again at final stage for scaling. Also image scaler increased efficiency of IP by using serial divider to calculate parameters by itself. Parameters used in image scaling is automatically produced by it. Suggested methods are designed by Verilog HDL and implemented with Xilinx Vertex-4 XC4LX80 and ASIC using TSMC 0.18um process.

• Journal of Biosystems Engineering
• /
• v.27 no.6
• /
• pp.479-490
• /
• 2002

A dynamic model of a power shuttle transmission was developed and its validity was verified using the experimental data obtained from a transmission test bench. A 40㎾, 4WD tractor was also modeled using an application software EASY5 to investigate parameters and their effects on the power shifting performance. For a tractor model, the manual reverse gear was replaced by a power shuttle transmission. The tractor model also included an engine, main-gears for transmission, wheels, differentials and planet gears. Using the tractor model, the effects of the parameters such as modulating pressure and time, engine speed, tractor speed. tractor weight. reverse to forward speed ratio and torsional damper on the transient characteristics at starting and shuttle shifting were investigated by the computer simulation. The transient characteristics were represented by variations in clutch pressure, torque transmitted to input shaft and driving wheels, and power transmission capacity of the clutch. It was found that the modulating pressure and time affected most significantly the torque transmission and shifting time. The input torque, axle torque, power transmission capacity of the clutch and transmission time all increased with increase in engine speed, tractor speed. tractor weight and ratio of reverse to forward speeds. However, the axle torque decreased with tractor speed. Both the axle torque and power transmission capacity of the clutch also decreased with the ratio of reverse to forward speeds.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.3
• /
• pp.171-177
• /
• 2007

In this paper, we have designed and implemented an optical signal processor in order to use in a fiber-optic current CT for electric equipments where its properties were discussed. The fabricated optical signal processor is used to reduce a measurement current error that induced by the effects of intensity variation in the optical output signal due to losses coming from optical components or polarization variation in a PFOCS. Also, the optical signal processor was fabricated in compact/lightweight with unification of opto-electronic transducer part, analog signal process part, and real-time measurement part consisted of a level shift and ${\mu}-processor$. The experiment of optical signal processor has been performed in the range of $0{\sim}7,500A$ using the PFOCS made all fiber-optic components. As a result of experiment, the linearity error of measurement current is less than 1.7% and its average error is less than 0.3% in the range of $1,000A{\sim}7,000A$.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.2
• /
• pp.144-150
• /
• 1990

This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.

• The Journal of the Acoustical Society of Korea
• /
• v.21 no.5
• /
• pp.446-454
• /
• 2002

This paper presents the Doppler Scanning technique which enables us to detect the relative positions of moving distributed sources using Doppler frequency shift estimate when the moving source consists of distributed sources with different signature frequencies. Doppler frequency shifts of characteristic frequencies of machinery noise sources such as ship's generator and propeller, with tine along CPA (Closest Point of Approach of moving source) are unique, and can be functioned with respect to each source position. Therefore, this technique can be applied to estimate the relative geometrical positions between machinery noise sources. The Extended Kalman Filter (EKF) which has a high frequency resolution with high time resolution, is adopted for improving accuracy of Doppler frequency shift estimate geometric resolution of machinery positions since machinery noise sources show in general low frequency band characteristics with limited spacial distance. The performance of the technique is examined by the numerical simulations and is verified by the experiment using loudspeaker sources on the roof of the car.