• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.47 no.4
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• pp.283-288
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• 2019

In this paper, there is summarized the validation of ground test results through the telemetry acquired during on-orbit initial activation on solar-array drive assembly(SDA) of GK2A launched at Dec-5, 2018. Especially, the decision logic of SDA initial position and the compensation logic are validated and confirmed. The SDA initial position is needed when GK2A enter to geostationary orbit from transfer orbit and the compensation logic is for the accumulated position error due to the open-loop control. Up to now, it is normal operating. Also the periodic offset between the geostationary orbit and Sun position is found that it is not checked on design phase, and then the proper threshold value is applied.

• The KIPS Transactions:PartD
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• v.19D no.2
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• pp.161-186
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• 2012

Recently, the flash memory consistently increases the storage capacity while the price of the memory is being cheap. This makes the mass storage SSD(Solid State Drive) popular. The flash memory, however, has a lot of defects. In order that these defects should be complimented, it is needed to use the FTL(Flash Translation Layer) as a special layer. To operate restrictions of the hardware efficiently, the FTL that is essential to work plays a role of transferring from the logical sector number of file systems to the physical sector number of the flash memory. Especially, the poor performance is attributed to Erase-Before-Write among the flash memory's restrictions, and even if there are lots of studies based on the log block, a few problems still exists in order for the mass storage flash memory to be operated. If the FAST based on Log Block-Based Flash often is generated in the wide locality causing the random writing, the merge operation will be occur as the sectors is not used in the data block. In other words, the block thrashing which is not effective occurs and then, the flash memory's performance get worse. If the log-block makes the overwriting caused, the log-block is executed like a cache and this technique contributes to developing the flash memory performance improvement. This study for the improvement of the random writing demonstrates that the log block is operated like not only the cache but also the entire flash memory so that the merge operation and the erase operation are diminished as there are a distinct mapping table called as the offset mapping table for the operation. The new FTL is to be defined as the XAST(extensively-Associative Sector Translation). The XAST manages the offset mapping table with efficiency based on the spatial locality and temporal locality.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5A
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• pp.432-440
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• 2011

For the 4th generation mobile communication, LTE-advanced system needs the broad frequency band up to 100MHz for providing the data rate of maximum 1Gpbs. However, it is very difficult to secure the broad frequency band in the current frequency allocation situation. So, carrier aggregation was proposed as the solution, in which several fragmented frequency bands are used at the same time. Basically, multiple parallel receivers are required to get the information data from the different frequency bands but this conventional multi-chain receiver system is very inefficient. Therefore, in this paper, we like to study the single chain system that is able to receive the multi-band signals in a single receiver based on the time division multiplexing (TDM) reception method. This proposed TDM receiver efficiently manage to receive the multi-band signals in time domain and handle the baseband signals with one DSP board. However, the serious distortion could be generated by the sampling timing offset (STO) in the TDM-based system. Therefore, we like to analyze STO effects in the TDM-based system and propose a compensation method using estimated STO. Finally, it is shown by simulation that the proposed method is appropriate for the single chain receiver and show good compensation performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.