• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.13-22
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• 1998

In this paper, we propose a high-performance BICS(built-in current sensor) which is fabricated in 0.8${\mu}{\textrm}{m}$ single-poly two-metal process for IDDQ testing of CMOS VLSI circuit. The CUT(circuit under test) is 4-bit full adder with a bridging fault. Using two nMOSs that have different size, two bridging faults that have different resistance values are injected in the CUT. And controlling a gate node, we experimented various fault effects. The proposed BICS detects the faulty current at the end of the clock period, therefore it can test a CUT that has a much longer critical propagation delay time and larger area than conventional BICSs. As expected in the HSPICE simulation, experimental results of fabricated chip demonstrated that the proposed BICS can exactly detect bridging faults in the circuit.

• The KIPS Transactions:PartC
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• v.14C no.4
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• pp.349-358
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• 2007

Ethernet Passive Optical Network(EPON), which is one of PON technologies for realizing FTTx(Fiber-To-The-Curb/Home/Office), can cost-effectively construct optical access networks. In addition, EPON can provide high transmission rate up to 10Gbps and it is compatible with existing customer devices equipped with Ethernet card. To effectively control frame transmission from ONUs to OLT EPON can use Multi-Point Control Protocol(MPCP) with additional control functions in addition to Media Access Control(MAC) protocol function. For EPON, many researches on intra- and inter-ONU scheduling algorithms have been performed. Among the inter-ONU scheduling algorithms, IPS(Interleaved Polling with Stop) based on polling scheme is efficient because OLT assigns available time portion to each ONU given the request information from all ONUs. Since the IPS needs an idle time period on uplink between two consecutive frame transmission periods, it wastes time without frame transmissions. In this paper, we propose a dynamic bandwidth allocation algorithm to increase the channel utilization on uplink and evaluate its performance using simulations. The simulation results show that the proposed Two-phase Cycle Danamic Bandwidth Allocation(TCDBA) algorithm improves the throughput about 15%, compared with the IPS and Fast Gate Dynamic Bandwidth Allocation(FGDBA). Also, the average transmission time of the proposed algorithm is lower than those of other schemes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2637-2642
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• 2015

The low-density parity check(LDPC) code is being widely used due to its outperformed error-correction ability. The decoder of the quasi-cyclic LDPC(QC-LDPC) codes, a kind of LDPC codes, requires a multi-size cyclic shifter(MSCS) performing rotation of various sizes. The MSCS can be implemented with a Benes network, which requires a $3{\times}3$ switch if the number of data to be rotated is a multiple of 3. This paper proposes a control signal generation with lower complexity and a faster $3{\times}3$ switch. For the experiment, the proposed schemes are applied to the MSCS of an IEEE 802.16e WiMAX QC-LDPC code decoder. The result shows that the delay is reduced by about 8.7%.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.124-131
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• 2014

This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.2 s.179
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• pp.43-50
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• 2006

Recently, with rapid development of semiconductor and flat panel display, the manufacturing equipments are required to have large travel range, high productivity, and high accuracy. In this paper, an ultra precision decoupled dual servo (DDS) system is proposed to meet these requirements. And a control scheme for the DDS is studied. The proposed DDS consists of a $XY{\Theta}$ fine stage for handling work-pieces precisely and a XY coarse stage for large travel range. The fine stage consists of four voice coil motors (VCM) and air bearing guides. The coarse stage consists of linear motors and air bearing guides. The DDS is mechanically decoupled between coarse stage and fine stage. Therefore, both stages must be controlled independently and the performance of the DDS is mainly determined by the fine stage. For high performance tracking, the controller of fine stage consists of time delay control (TDC) and perturbation observer while the controller of coarse stage is TDC alone. With these individual controllers, two kinds of dual-servo control strategies are suggested: master-slave type and parallel type. By simulations and experiments, the performances of two dual-servo control strategies are compared.

• The Journal of Korea Robotics Society
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• v.11 no.4
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• pp.277-284
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• 2016

A new prediction scheme has been proposed for the robust teleoperation in a non-visible environment. The positioning error caused by the time delay in the non-visible environment has been compensated for by the Smith predictor and the sensory data have been estimated by the Grey model. The Smith predictor is effective for the compensation of the positioning error caused by the time delay with a precise system model. Therefore the dynamic model of a mobile robot has been used in this research. To minimize the unstable and erroneous states caused by the time delay, the estimated sensor data have been sent to the operator. Through simulations, the possibility of compensating the errors caused by the time delay has been verified using the Smith predictor. Also the estimation reliability of the measurement data has been demonstrated. Robust teleoperations in a non-visible environment have been performed with a mobile robot to avoid the obstacles effective to go to the target position by the proposed prediction scheme which combines the Smith predictor and the Grey model. Even though the human operator is involved in the teleoperation loop, the compensation effects have been clearly demonstrated.

• Journal of Biomedical Engineering Research
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• v.19 no.3
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• pp.313-320
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• 1998

Tri-phasic pulsatile flow is the general flow pattern of human circulary system. In emulating the various situation of cardiovascular system, it is essential to make tri-phasic source flow. To emulate tri-phasic pulsatile flow, we used electro-hydronic style LVAD(Left Ventricular Assist Device) with glass phantom and rubber tube. We have selected control parameters and examined the changing effect of each parameter by using Doppler ultrasound. In this experiment, it was shown that the distal compliance and the break time were the major factors to form tri-phasic flow. The results make it possible to emulate and explain the various situation of human vascular system. In this point, this results will be an useful method in the clinic application.

• Journal of the Korean Society of Propulsion Engineers
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• v.10 no.3
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• pp.109-117
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• 2006

Hot firing performance test of hydrazine decomposition catalyst used for monopropellant thruster of satellite and launch vehicle was performed on the ground. A test equipment for hot firing performance measurement of catalyst test was developed in collaboration with Hanwha Corp., and the catalyst firing performance were tested with the equipment. After a reaction delay time, a catalyst activity and a granule stability were measured for 2 times, satisfactory results were obtained such as 25msec, 2%, $704^{\circ}C$ for each test items on the average. In addition, the current development status of domestic prototype catalyst and its decomposition performance test results are presented.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.3-11
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• 2000

In this paper, we design modular multiplication systolic array and exponentiation processor having n bits message black. This processor uses Montgomery algorithm and LR binary square and multiply algorithm. This processor consists of 3 divisions, which are control unit that controls computation sequence, 5 shift registers that save input and output values, and modular exponentiation unit. To verify the designed exponetion processor, we model and simulate it using VHDL and MAX+PLUS II. Consider a message block length of n=512, the time needed for encrypting or decrypting such a block is 59.5ms. This modular exponentiation unit is used to RSA cryptosystem.