• Journal of IKEEE
• /
• v.22 no.3
• /
• pp.522-531
• /
• 2018

A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

• Education of Primary School Mathematics
• /
• v.25 no.1
• /
• pp.57-79
• /
• 2022

Current mathematics It is necessary to ensure that ratio and proportion concept is not distorted or broken while being treated as if they were easy to teach and learn in school. Therefore, the purpose of this study is to analyze the activities presented in the textbook. Based on prior work, this study reinterpreted the proportional reasoning task from the proportional perspective of Beckmann and Izsak(2015) to the multiplicative structure of Vergnaud(1996) in four ways. This compared how they interpreted the multiplicative structure and relationships between two measurement spaces of ratio and rate units and proportional expression and proportional distribution units presented in the revised textbooks of 2007, 2009, and 2015 curriculum. First, the study found that the proportional reasoning task presented in the ratio and rate section varied by increasing both the ratio structure type and the proportional reasoning activity during the 2009 curriculum, but simplified the content by decreasing both the percentage structure type and the proportional reasoning activity. In addition, during the 2015 curriculum, the content was simplified by decreasing both the type of multiplicative structure of ratio and rate and the type of proportional reasoning, but both the type of multiplicative structure of percentage and the content varied. Second, the study found that, the proportional reasoning task presented in the proportional expression and proportional distribute sections was similar to the previous one, as both the type of multiplicative structure and the type of proportional reasoning strategy increased during the 2009 curriculum. In addition, during the 2015 curriculum, both the type of multiplicative structure and the activity of proportional reasoning increased, but the proportional distribution were similar to the previous one as there was no significant change in the type of multiplicative structure and proportional reasoning. Therefore, teachers need to make efforts to analyze the multiplicative structure and proportional reasoning strategies of the activities presented in the textbook and reconstruct them according to the concepts to teach them so that students can experience proportional reasoning in various situations.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.47 no.1
• /
• pp.139-149
• /
• 2010

Random scalar countermeasures, which carry out the scalar multiplication by the ephemeral secret key, against the differential power analysis of ECIES and ECDH have been known to be secure against various power analyses. However, if an attacker can find this ephemeral key from the one power signal, these countermeasures can be analyzed. In this paper, we propose a new power attack method which can do this analysis. Proposed attack method can be accomplished while an attacker compares the elliptic curve doubling operations and we use the principle component analysis in order to ease this comparison. When we have actually carried out the proposed power analysis, we can perfectly eliminate the error of existing function for the comparison and find a private key from this elimination of the error.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2002.11a
• /
• pp.63-68
• /
• 2002

JPEG2000은 기존의 정지영상압축부호화 방식에 비해 우수한 비트율-왜곡(Rate-Distortion)특성과 향상된 주관적 화질을 제공하며 인터넷, 디지털 영상카메라, 이동단말기, 의학영상 등 다양한 분야에서 적용될 수 있는 새로운 정지영상압축 표준이다. 본 논문에서는 SoC(System on a Chip)설계를 고려한 JPEG2000 인코더의 구조를 제안하고 IP(Intellectual Property)를 설계 및 검증하였다. 구현된 JPEG2000 IP는 DWT(Discrete Wavelet Transform)블록, 스칼라양자화블록, EBCOT(Embedded Block Coding with Optimized Truncation)블록으로 구성되어 있다. IP는 모의실험을 통해 구현 구조에 대한 타당성을 검증하였고, 반도체설계자산연구센터에서 제시한 'RTL Coding Guideline'에 따라 HDL을 설계하였다. 특히, DWT블록은 구현시 많은 연산과 메모리 용량이 필요하므로 영상을 저장할 외부 메모리를 사용하였고, 빠른 곱셈과 덧셈연산을 위한 3단 파이프라인 부스곱셈기(3-state pipeline booth multiplier)와 캐리예측 덧셈기(carry lookahead adder)를 사용하였다. 설계된 JPEG2000 IP들은 삼성 0.35$\mu\textrm{m}$ 라이브러리를 이용하여 Synopsys사 Design Analyzer 틀을 통해 논리 합성하였으며, Xillinx 100만 게이트 FPGA칩에 구현하여 그 동작을 검증하였다. 또한, Hard IP 설계를 위해 Avanti사의 Apollo툴을 이용하여 Layout을 수행하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.10a
• /
• pp.190-192
• /
• 2018

This paper describes a design of an elliptic curve cryptography (ECC) processor that supports five pseudo-random curves and five Koblitz curves over binary field defined by the NIST standard. The ECC processor adopts the Lopez-Dahab projective coordinate system so that scalar multiplication is computed with modular multiplier and XORs. A word-based Montgomery multiplier of $32-b{\times}32-b$ was designed to implement ECCs of various key lengths using fixed-size hardware. The hardware operation of the ECC processor was verified by FPGA implementation. The ECC processor synthesized using a 0.18-um CMOS cell library occupies 10,674 gate equivalents (GEs) and 9 Kbits RAM at 100 MHz, and the estimated maximum clock frequency is 154 MHz.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.174-179
• /
• 2021

An Edwards curve cryptography (EdCC) core supporting point scalar multiplication (PSM) on Edwards curves of Edwards25519 and Edwards448 was designed. For area-efficient implementation, finite field multiplier based on word-based Montgomery multiplication algorithm was designed, and the extended twisted Edwards coordinates system was adopted to implement point operations without division operation. As a result of synthesizing the EdCC core with 100 MHz clock, it was implemented with 24,073 equivalent gates and 11 kbits RAM, and the maximum operating frequency was estimated to be 285 MHz. The evaluation results show that the EdCC core can compute 299 and 66 PSMs per second on Edwards25519 and Edwards448 curves, respectively. Compared to the ECC core with similar structure, the number of clock cycles required for 256-bit PSM was reduced by about 60%, resulting in 7.3 times improvement in computational performance.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
• /
• 2006.06a
• /
• pp.356-360
• /
• 2006

Recently, many power analysis attacks have been proposed. Since the attacks are powerful, it is very important to implement cryptosystems securely against the attacks. We propose countermeasures against power analysis attacks for elliptic curve cryptosystems based on Koblitz curves (KCs), which are a special class of elliptic curves. That is, we make our countermeasures be secure against SPA, DPA, and new DPA attacks, specially RPA, ZPA, using a random point at each execution of elliptic curve scalar multiplication. And since our countermeasures are designed to use the Frobenius map of KC, those are very fast.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.18 no.3
• /
• pp.323-328
• /
• 2008

This paper presents a Digital Signal Processor achieving high through-put for both decision intensive and computation intensive tasks. The proposed processor employees a multiplier, two ALU and load/store. Unit as operational units. Those four units are controlled and works parallel by superscalar control scheme, which is different from prior DSP architecture. The performance evaluation was done by implementing AC-3 decoding algorithm and 37.8% improvement was achieved. This study is valuable especially for the consumer electronics applications, which require very low cost.

• Journal of Institute of Convergence Technology
• /
• v.8 no.1
• /
• pp.15-20
• /
• 2018

Recently a GPU has acquired programmability to perform general purpose computation fast by running thousands of threads concurrently. This paper presents a parallel GPU computation algorithm for dense matrix-matrix addition and scalar multiplication using OpenGL compute shader. It can play a very important role as a fundamental building block for many high-performance computing applications. Experimental results on NVIDIA Quad 4000 show that the proposed algorithm runs 21 times faster than CPU algorithm and achieves performance of 16 GFLOPS in single precision for dense matrices with size 4,096. Such performance proves that our algorithm is practical for real applications.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.9 no.1
• /
• pp.85-102
• /
• 1999

In this paper, we propose an EC-SRP(Elliptic Curve - Secure Remote Password) protocol that uses ECDLP(Elliptic Curve Discrete Logarithm Problem) instead SRP protocols’s DLP. Since EC-SRP uses ECDLP, it inherits the high performance and security those are the properties of elliptic curve. And we reduced the number of elliptic curve scalar multiplication to improve EC-SRP protocol’s performance. Also we have proved BC-SRP protocol is a secure AKC(Authenticated Key Agreement with Key Confirmation) protocol in a random oracle model.