• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.947-960
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• 1996

The primary goal for developing high performance ATM switching systems is to minimized the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLIS(Very Large Scale Integrated circuit) as the number of input ports increased, the used of switching module method the realizes 32$\times$32, 150 Mb/s switch utilizing 8$\times$8, 600Mb/s os 16$\times$16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evalu ated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure in outline of 32$\times$32(4.9Gb/s throughput), 150Mb/s switches under research in many countries is proposed, and eventually, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.429-432
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• 2004

In this paper, we propose a new sorting algorithm for ATM switch with a shared buffer which has a sequencer architecture with single queue. The proposed switch performs a sorting procedure of ATM cell based on the output port number of ATM cell with hardware implementation. The proposed architecture has a single buffer physically but logically it has function of multi-queue which is designed at most to control the conflicts in output port. In the future, this architecture will take various applications for routing switch and has flexibility for the extension of system structure. therefore, this structure is expected on good structure in effective transmission.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.373-376
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• 2003

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4B
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• pp.162-169
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• 2005

Network traffic measurements show that the data traffic on packet switched networks has the self-similar features which is different from the traditional traffic models such as Poisson distribution or Markovian process model. Most of the call admission control researches have been done on the performance analysis of a single network switch. It is necessary to consider the performance analysis of the proposed admission control scheme under interconnected switch environment because the data traffic transmits through switches in networks. From the simulation results, it is shown that the call admission control scheme may not operate properly on the interconnected switch even though the scheme works well on a single switch. In this parer, we analyze the cell loss probability, utilization and self-similarity of output ports of the interconnected networks switch by using shared buffer memory management schemes and propose the new call admission control scheme considering the interconnected network switches under self-similar traffic environments.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.1197-1200
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• 2002

본 논문에서는 GFR이 요구하는 최소 전송률 보장과 높은 공평성을 제공하기 위하여 퍼지 이론을 이용한 버퍼관리 알고리즘을 제안하였다. 제안된 알고리즘은 태깅정보, 전체 버퍼의 점유량, VC의 부하 정도로 구성된 세 개의 파라미터를 이용하여 패킷 폐기를 결정한다. 시뮬레이션 결과 MCR의 크기가 커질수록 제안된 알고리즘의 수율과 공평성이 우수하였으며. 스위치에서 버퍼의 크기 변화에서도 Double-EPD나 DFRA는 비슷한 성능을 보였고, 제안된 알고리즘은 좋은 수율과 공평성을 제공한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.291-294
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• 2004

In this paper, we consider the broadcast switch architecture for hish performance multicast packet switching. In input and output buffered switch, we propose a new switch architecture which supports high throughput in broadcast packet switching with switch planes of single input and multiple output crossbars. The proposed switch architecture has a central arbiter that arbitrates requests from plural input ports and generates multiple grant signals to multiple output ports in a packet transmission slot. It provides high speed pipelined arbitration and large scale switching capacity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1910-1916
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• 1999

This paper suggested to solve ATM switch performance and service rate which was input buffer managed scheme in ATM network with burst traffic characteristics, For this purpose, ATM multiplexer is prepared before sending for handling burst random input traffic to multiplex and then sort based on cell inter-arrival time and cell processing due time which had been marked after that. The server looks for cell header with the most shortest due time and sends it, thus it is satisfied that real time traffic for instance CBR and rt-VBR was guaranteed cell processing time to send fast than non real time traffic. For analysis of ATM switch performance with cell processing due time and priority, each output port has divided into four different virtual buffer and each buffer has assigned different cell inter-arrival time and processing due time according to ATM Forum for example CBT/rt-VBR, nrt-VBR, ABR and UBR and showed it’s optimal service parameters then analyzed service rate behaviors according to each traffic characteristics.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.411-413
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• 1999

본 논문에선느 ATM 통신망을 위한 여러 ATM 스위치 모델들 중에서, 내부적으로 블록킹(blocking)이 없고 입출력 단에 각각 버퍼가 할당되어 있는 입출력 버퍼형 교환기에 대하여 연구하였다. 기존에서 스위치 스피드-업(Switch Speed-up) 기법하에서 주로 연구가 이루어졌다. 따라서, 본 논문에서는 유니폼 트래픽하에서 Output-port Expansion 기법을 사용한 귀환.손실 모드 및 하이브리드 모드하에서의 셀 손실률을 비교 분석하였다. Output-port Expansion 기법은, 한 타임 슬롯동안에 입력포트 당 하나의 셀만 교환되며, 만약 하나 이상의 셀들이 같은 출력포트로 향하면, 최대 교환되는 셀 수를 K(Output-port Expansion Ratio)개로 제한하는 방식이다. 유니폼 트래픽(uniform random traffic) 하에서 각 모드에 따른 셀 손실률을 비교 분석한 결과, 로드 0.9를 기점으로, 0.9이하의 로드에서는 하이브리드 모드가, 0.9이상의 로드에서는 손실모드가 가장 낮은 셀 손실률을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.7B
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• pp.1236-1243
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• 2000

본 논문은 LAN의 대역폭을 증가 시키기 위하여, 여러 개의 링크를 논리적인 하나의 링크처럼 동작하도록 하는 다중링크통함(link aggregation)기술에 대한 것이다. 우리는 망 구성에 따라 이 기술의 동작방식이 상이함에 착안하여, 두 가지의 새로운 프레임 분배방식을 제안하고 SIMULA를 이용한 모의실험으로 성능을 분석하였다. 먼저, LAN스위치와 스위치간에 적용 가능한 동적 프로엠 분배방식을 제안하였다. 이 방식은 특정 포트로 집중되는 프레임들을 분산시키기 위하여 가장 이용율이 낮은 링크를 동적으로 추가하는 것으로서, 링크 추가시 프레임들의 전달순서를 지킬 수 있도록 특별한 플러쉬 버퍼를 사용하였다. 모의실험 결과, 프러임간의 순서가 유지되면서도 스위치의 내부 버퍼에서의 프레임 폐기율이 기존 방식에 비해 감소됨을 확인하였다. 그리고, 단말과 단말간에 다중링크가 사용된 경우, 수신된 프레임들 간의 순서 뒤바뀜 문제에 대한 해결책으로 패딩 방법과, 태깅 방법, 프레임 분할 방식 등의 세가지으 프레임 분배방식을 제안하고 성능을 분석하였다. 이러한 세가지 방법 중에서 프레임 분할방식이 가장 성능면에서 우수함이 모의실험결과\ulcorner서 알 수 있지만, 패딘 방식도 구현관점에서 장점이 있다.

• Journal of the Korea Society of Computer and Information
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• v.11 no.1 s.39
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• pp.157-165
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• 2006

This paper proposes a new output-buffered multicast ATM switch with tandem crosspoints switching fabric, named the MTCOS(Multicast Tandem Crosspoint Output-buffered Switch). The MTCOS consists of multiple simple crosspoint switch fabrics, named TCSF(Tandem Crosspoint Switch Fabric) , and concentrated output buffers for efficient multicasting. The TCSF resolves the cell delay deviation problem which the self-routing crossbar switches inherently have. Further, it offers multiple concurrent pathes from one input to multiple output ports. It also provides multi-channel switching by easy software configuration and has several desirable characteristics such as scalability, high Performance, and modularity. A shared traffic concentration and output queuing strategies of the MTCOS results in lower cell loss as well as lower cell delay time over a wide range of multicast traffic. Furthermore, it has lower hardware complexity than that of the SCOQ and Knockout multicast switch to achieve the same Knockout concentration rate as the conventional switches. It is shown that the proposed switch can be easily applied to design high performance for any multicast traffic by analytic analysis and computer simulation.